On Fri, Dec 07, 2018 at 07:13:05PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 06, 2018 at 02:23:00PM +0200, Imre Deak wrote:
> > On Wed, Dec 05, 2018 at 10:20:23PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > The DMC firmware is confused and forces on the BIOS and debug
> > >
On Thu, Dec 06, 2018 at 02:23:00PM +0200, Imre Deak wrote:
> On Wed, Dec 05, 2018 at 10:20:23PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The DMC firmware is confused and forces on the BIOS and debug
> > power well requests for PW1 and MISC IO on some platforms. On
> > BXT I mea
On Thu, Dec 06, 2018 at 02:23:00PM +0200, Imre Deak wrote:
> On Wed, Dec 05, 2018 at 10:20:23PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The DMC firmware is confused and forces on the BIOS and debug
> > power well requests for PW1 and MISC IO on some platforms. On
> > BXT I mea
On Wed, Dec 05, 2018 at 10:20:23PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The DMC firmware is confused and forces on the BIOS and debug
> power well requests for PW1 and MISC IO on some platforms. On
> BXT I measured this to waste about 10mW in the freeze system
> suspend state wit
From: Ville Syrjälä
The DMC firmware is confused and forces on the BIOS and debug
power well requests for PW1 and MISC IO on some platforms. On
BXT I measured this to waste about 10mW in the freeze system
suspend state with the SoC in s0. I didn't get conclusive
numbers for s0ix on account of the
