Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7109
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Fri, Aug 07, 2015 at 03:30:12PM +0100, Siluvery, Arun wrote:
> On 07/08/2015 12:52, Daniel Vetter wrote:
> >On Fri, Aug 07, 2015 at 11:15:56AM +0300, Mika Kuoppala wrote:
> >>Daniel Vetter writes:
> >>
> >>>On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
> If idle to active b
On 07/08/2015 12:52, Daniel Vetter wrote:
On Fri, Aug 07, 2015 at 11:15:56AM +0300, Mika Kuoppala wrote:
Daniel Vetter writes:
On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
If idle to active bit is set, the rest of the fields
in CSQ are not valid.
Bail out early if this is
On Fri, Aug 07, 2015 at 11:15:56AM +0300, Mika Kuoppala wrote:
> Daniel Vetter writes:
>
> > On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
> >> If idle to active bit is set, the rest of the fields
> >> in CSQ are not valid.
> >>
> >> Bail out early if this is the case in order t
Daniel Vetter writes:
> On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
>> If idle to active bit is set, the rest of the fields
>> in CSQ are not valid.
>>
>> Bail out early if this is the case in order to prevent
>> rest of the loop inspecting stale values.
>>
>> Signed-off-by:
On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
> If idle to active bit is set, the rest of the fields
> in CSQ are not valid.
>
> Bail out early if this is the case in order to prevent
> rest of the loop inspecting stale values.
>
> Signed-off-by: Mika Kuoppala
Same questions he
If idle to active bit is set, the rest of the fields
in CSQ are not valid.
Bail out early if this is the case in order to prevent
rest of the loop inspecting stale values.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/dr
