[Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT

2015-03-02 Thread Gaurav K Singh
On CHT, changes are required for calculating the correct m,n & p with minimal error +/- for the required DSI clock, so that the correct dividor & ctrl values are written in cck regs for DSI. This patch has been tested on CHT RVP with 1200 x 1920 panel. Signed-off-by: Gaurav K Singh --- drivers/g

Re: [Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT

2015-01-16 Thread Daniel Vetter
On Thu, Jan 15, 2015 at 01:25:02PM +0200, Jani Nikula wrote: > On Wed, 14 Jan 2015, "Singh, Gaurav K" wrote: > > On 12/12/2014 1:03 PM, Singh, Gaurav K wrote: > >> > >> On 12/10/2014 7:38 PM, Gaurav K Singh wrote: > >>> For CHT changes are required for calculating the correct m,n & p with > >>> mi

Re: [Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT

2015-01-15 Thread Jani Nikula
On Wed, 14 Jan 2015, "Singh, Gaurav K" wrote: > On 12/12/2014 1:03 PM, Singh, Gaurav K wrote: >> >> On 12/10/2014 7:38 PM, Gaurav K Singh wrote: >>> For CHT changes are required for calculating the correct m,n & p with >>> minimal error +/- for the required DSI clock, so that the correct >>> divi

Re: [Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT

2015-01-14 Thread Singh, Gaurav K
On 12/12/2014 1:03 PM, Singh, Gaurav K wrote: On 12/10/2014 7:38 PM, Gaurav K Singh wrote: For CHT changes are required for calculating the correct m,n & p with minimal error +/- for the required DSI clock, so that the correct dividor & ctrl values are written in cck regs for DSI. This patch

Re: [Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT

2014-12-19 Thread Jani Nikula
On Wed, 10 Dec 2014, Gaurav K Singh wrote: > For CHT changes are required for calculating the correct m,n & p with > minimal error +/- for the required DSI clock, so that the correct dividor > & ctrl values are written in cck regs for DSI. This patch has been tested > on CHT RVP with 1200 x 1920 p

Re: [Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT

2014-12-11 Thread Singh, Gaurav K
On 12/10/2014 7:38 PM, Gaurav K Singh wrote: For CHT changes are required for calculating the correct m,n & p with minimal error +/- for the required DSI clock, so that the correct dividor & ctrl values are written in cck regs for DSI. This patch has been tested on CHT RVP with 1200 x 1920 panel

Re: [Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT

2014-12-10 Thread shuang . he
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1 364/364 3

[Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT

2014-12-10 Thread Gaurav K Singh
For CHT changes are required for calculating the correct m,n & p with minimal error +/- for the required DSI clock, so that the correct dividor & ctrl values are written in cck regs for DSI. This patch has been tested on CHT RVP with 1200 x 1920 panel. Signed-off-by: Gaurav K Singh --- drivers/g