Hi
2012/11/1 Daniel Vetter :
> We need to set the timing override chicken bit after fdi link training
> has completed and before we enable the dp transcoder. We also have to
> clear that bit again after disabling the pch dp transcoder.
>
> See "Graphics BSpec: vol4g North Display Engine Registers
On Thu, 1 Nov 2012 16:33:45 +0100
Daniel Vetter wrote:
> On Thu, Nov 01, 2012 at 07:37:36AM -0700, Jesse Barnes wrote:
> > > v3: Paulo Zanoni pointed out that this workaround is also required on
> > > the LPT PCH. And Arthur Ranyan confirmed that this workaround is
> > > requierd for all ports on
On Thu, Nov 01, 2012 at 07:37:36AM -0700, Jesse Barnes wrote:
> > v3: Paulo Zanoni pointed out that this workaround is also required on
> > the LPT PCH. And Arthur Ranyan confirmed that this workaround is
> > requierd for all ports on the pch, not just DP: The important part
> > is that the bit is
On Thu, 1 Nov 2012 09:15:30 +0100
Daniel Vetter wrote:
> We need to set the timing override chicken bit after fdi link training
> has completed and before we enable the dp transcoder. We also have to
> clear that bit again after disabling the pch dp transcoder.
>
> See "Graphics BSpec: vol4g No
We need to set the timing override chicken bit after fdi link training
has completed and before we enable the dp transcoder. We also have to
clear that bit again after disabling the pch dp transcoder.
See "Graphics BSpec: vol4g North Display Engine Registers [IVB],
Display Mode Set Sequence" and "
