Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl.

2017-10-23 Thread Ville Syrjälä
On Fri, Oct 20, 2017 at 03:15:49PM -0700, Rodrigo Vivi wrote: > Wa Display #1183 was recently added to workaround > "Failures when enabling DPLL0 with eDP link rate 2.16 > or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz > (CDCLK_CTL CD Frequency Select 10b or 11b) used in this > enabling o

[Intel-gfx] [PATCH] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl.

2017-10-20 Thread Rodrigo Vivi
Wa Display #1183 was recently added to workaround "Failures when enabling DPLL0 with eDP link rate 2.16 or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz (CDCLK_CTL CD Frequency Select 10b or 11b) used in this enabling or in previous enabling." This Workaround was designed to minimize the i

Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl.

2017-10-19 Thread Rodrigo Vivi
On Tue, Oct 17, 2017 at 07:25:46PM +, Ville Syrjälä wrote: > On Tue, Oct 17, 2017 at 10:38:19AM -0700, Rodrigo Vivi wrote: > > Wa Display #1183 was recently added to workaround > > "Failures when enabling DPLL0 with eDP link rate 2.16 > > or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz

Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl.

2017-10-17 Thread Rodrigo Vivi
On Tue, Oct 17, 2017 at 07:25:46PM +, Ville Syrjälä wrote: > On Tue, Oct 17, 2017 at 10:38:19AM -0700, Rodrigo Vivi wrote: > > Wa Display #1183 was recently added to workaround > > "Failures when enabling DPLL0 with eDP link rate 2.16 > > or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz

Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl.

2017-10-17 Thread Ville Syrjälä
On Tue, Oct 17, 2017 at 10:38:19AM -0700, Rodrigo Vivi wrote: > Wa Display #1183 was recently added to workaround > "Failures when enabling DPLL0 with eDP link rate 2.16 > or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz > (CDCLK_CTL CD Frequency Select 10b or 11b) used in this > enabling o

[Intel-gfx] [PATCH] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl.

2017-10-17 Thread Rodrigo Vivi
Wa Display #1183 was recently added to workaround "Failures when enabling DPLL0 with eDP link rate 2.16 or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz (CDCLK_CTL CD Frequency Select 10b or 11b) used in this enabling or in previous enabling." However our code is already not following the