> -Original Message-
> From: Roper, Matthew D
> Sent: Saturday, December 2, 2023 5:38 AM
> To: Lobo, Melanie
> Cc: intel-gfx@lists.freedesktop.org; Heikkila, Juha-pekka pekka.heikk...@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Support FP16 compre
Hi Stan,
I discussed with Ville a little bit on IRC and wanted to reflect some
conversation here as review so that it could be accommodated in your
next revision for bigjoiner changes.
For bigjoiner cases to work correctly, when bigjoiner steals a CRTC
for using it as slave CRTC, the assumption i
On Fri, 4 Aug 2023 12:05:44 +0800
Zhenyu Wang wrote:
> 01.org is dead so replace old gvt link with current wiki page.
>
> Signed-off-by: Zhenyu Wang
> Acked-by: Jani Nikula
> ---
> MAINTAINERS | 2 +-
> drivers/gpu/drm/i915/Kconfig | 2 +-
> drivers/gpu/drm/i915/inte
On 17-Jan-24 11:31 PM, Jani Nikula wrote:
On Wed, 17 Jan 2024, "Sharma, Swati2" wrote:
Hi Ville,
On 25-Oct-23 6:29 PM, Ville Syrjälä wrote:
On Wed, Oct 18, 2023 at 04:24:00PM +0300, Stanislav Lisovskiy wrote:
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/displa
On Wed, 17 Jan 2024, "Sharma, Swati2" wrote:
> Hi Ville,
>
> On 25-Oct-23 6:29 PM, Ville Syrjälä wrote:
>> On Wed, Oct 18, 2023 at 04:24:00PM +0300, Stanislav Lisovskiy wrote:
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 4f6835a7
Hi Ville,
On 25-Oct-23 6:29 PM, Ville Syrjälä wrote:
On Wed, Oct 18, 2023 at 04:24:00PM +0300, Stanislav Lisovskiy wrote:
For validation purposes, it might be useful to be able to
force Bigjoiner mode, even if current dotclock/resolution
do not require that.
Lets add such to option to debugfs.
Hi Stan, Ville,
After Stan's refactor series for bigjoiner, along with Vidya's patch
that assigns master/slave for MST as well, do you anticipate more MST
specific
bigjoiner modeset sequence changes to properly call crtc enable
sequence for MST master slave?
Stan, when you send the next revision
On Fri, Oct 13, 2023 at 01:43:46PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 13, 2023 at 01:00:00AM +0530, vsrini4 wrote:
> > Patch calculates bigjoiner pipes in mst compute.
> > Patch also passes bigjoiner bool to validate plane
> > max size.
>
> I doubt this is sufficient. The modeset sequence i
On Wed, Dec 13, 2023 at 04:07:26PM -0800, Matt Roper wrote:
> On Mon, Dec 04, 2023 at 11:13:52AM -0300, Gustavo Sousa wrote:
> > Quoting Gustavo Sousa (2023-12-04 11:04:20-03:00)
> > >Quoting Matt Roper (2023-12-01 20:07:48-03:00)
> > >>On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
Hi Jonathan,
On Mon, Dec 18, 2023 at 06:33:44PM +, Cavitt, Jonathan wrote:
...
> > On Tue, Nov 28, 2023 at 08:25:05AM -0800, Jonathan Cavitt wrote:
> > > Never block for outstanding work on userptr object upon receipt of a
> > > mmu-notifier. The reason we originally did so was to immediately
Hi Jonathan,
On Tue, Nov 28, 2023 at 08:25:05AM -0800, Jonathan Cavitt wrote:
> Never block for outstanding work on userptr object upon receipt of a
> mmu-notifier. The reason we originally did so was to immediately unbind
> the userptr and unpin its pages, but since that has been dropped in
> com
-Original Message-
From: Andi Shyti
Sent: Monday, December 18, 2023 8:06 AM
To: Cavitt, Jonathan
Cc: intel-gfx@lists.freedesktop.org; Gupta, saurabhg
; chris.p.wil...@linux.intel.com
Subject: Re: [Intel-gfx] [PATCH] drm/i915/gem: Atomically invalidate userptr on
mmu-notifier
>
&
On Mon, Dec 04, 2023 at 11:13:52AM -0300, Gustavo Sousa wrote:
> Quoting Gustavo Sousa (2023-12-04 11:04:20-03:00)
> >Quoting Matt Roper (2023-12-01 20:07:48-03:00)
> >>On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
> >>> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote
On 12/11/2023 9:26 PM, Matt Roper wrote:
On Mon, Dec 11, 2023 at 05:08:48PM +0530, Kalvala, Haridhar wrote:
On 12/6/2023 1:54 AM, Matt Roper wrote:
On Tue, Dec 05, 2023 at 02:41:05PM +0530, Haridhar Kalvala wrote:
Enable Force Dispatch Ends Collection for DG2.
BSpec: 46001
Signed-off-by: H
On Mon, Dec 11, 2023 at 02:42:30PM +0100, Andrzej Hajda wrote:
> On 24.11.2023 08:53, Andrzej Hajda wrote:
> > Cursor size reduction is not supported since MTL.
> >
> > Signed-off-by: Andrzej Hajda
> > ---
> > drivers/gpu/drm/i915/display/intel_display_device.h | 2 +-
> > 1 file changed, 1 in
On Mon, Dec 11, 2023 at 05:08:48PM +0530, Kalvala, Haridhar wrote:
>
> On 12/6/2023 1:54 AM, Matt Roper wrote:
> > On Tue, Dec 05, 2023 at 02:41:05PM +0530, Haridhar Kalvala wrote:
> > > Enable Force Dispatch Ends Collection for DG2.
> > >
> > > BSpec: 46001
> > >
> > > Signed-off-by: Haridhar K
On 24.11.2023 08:53, Andrzej Hajda wrote:
Cursor size reduction is not supported since MTL.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/display/intel_display_device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Gently ping.
CC: maintainers
Regards
Andrzej
diff --gi
On 12/6/2023 1:54 AM, Matt Roper wrote:
On Tue, Dec 05, 2023 at 02:41:05PM +0530, Haridhar Kalvala wrote:
Enable Force Dispatch Ends Collection for DG2.
BSpec: 46001
Signed-off-by: Haridhar Kalvala
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_wor
On Wed, 06 Dec 2023, Gustavo Sousa wrote:
> Quoting Jani Nikula (2023-12-05 09:15:45-03:00)
>>Reduce the duplication.
>
> By the way, is it too ambitious to dream of a to_i915() using generics?
I'm not fundamentally opposed, but there are a few open questions here.
_Generic() has been slowly cro
On Tue, 05 Dec 2023, Rodrigo Vivi wrote:
> On Tue, Dec 05, 2023 at 02:15:45PM +0200, Jani Nikula wrote:
>> Reduce the duplication.
>>
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Rodrigo Vivi
Thanks, pushed to din.
BR,
Jani.
--
Jani Nikula, Intel
Xe needs intel_fb_bo_framebuffer_fini for taking care of unpinning the fb
and taking reference. In i915 this can be empty.
Also move intel_frontbuffer_get to be done after
intel_fb_bo_framebuffer_init to have reasonable sequences:
intel_fb_bo_framebuffer_init
intel_frontbuffer_get
...
intel_fron
Fail repeater authentication step in case RX_INFO indicates
HDCP1.x or HDCP2.0/2.1 device is present downstream in repeater
topology and content type set by userspace is Type1.
--v2
-Fix build error.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 7 +++
1 file
Hi Karthik,
On Fri, Dec 01, 2023 at 08:04:30PM +0530, Karthik Poosa wrote:
> Updated i915 hwmon with fixes for issues reported by static analysis tool.
> Fixed unintentional buffer overflow (OVERFLOW_BEFORE_WIDEN) with upcasting.
what kind of error was this? Was it caught by a static analyzer
or
://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:
https://lore.kernel.org/r/20231206093916.1733863-1-suraj.kandpal%40intel.com
patch subject: [Intel-gfx] [PATCH] drm/i915/hdcp: Fail Repeater authentication
if Type1 device not present
config: x86_64-defconfig
(https://download.01.org/0day-ci/archive
://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:
https://lore.kernel.org/r/20231206093916.1733863-1-suraj.kandpal%40intel.com
patch subject: [Intel-gfx] [PATCH] drm/i915/hdcp: Fail Repeater authentication
if Type1 device not present
config: x86_64-allyesconfig
(https://download.01.org/0day-ci/archive
Quoting Jani Nikula (2023-12-05 09:15:45-03:00)
>Reduce the duplication.
By the way, is it too ambitious to dream of a to_i915() using generics?
--
Gustavo Sousa
>
>Signed-off-by: Jani Nikula
>---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 24 ++--
> 1 file changed, 10 inser
Fail repeater authentication step in case RX_INFO indicates
HDCP1.x or HDCP2.0/2.1 device is present downstream in repeater
topology and content type set by userspace is Type1.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 7 +++
1 file changed, 7 insertions(+)
On Tue, Dec 05, 2023 at 02:41:05PM +0530, Haridhar Kalvala wrote:
> Enable Force Dispatch Ends Collection for DG2.
>
> BSpec: 46001
>
> Signed-off-by: Haridhar Kalvala
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
> 2 files c
From: Ville Syrjälä
On ADL+ the hardware automagically calculates the CCS AUX surface
stride from the main surface stride, so when remapping we can't
really play a lot of tricks with the main surface stride, or else
the AUX surface stride would get miscalculated and no longer
match the actual dat
On Tue, Dec 05, 2023 at 02:50:57PM +0200, Jani Nikula wrote:
> On Tue, 05 Dec 2023, "Shankar, Uma" wrote:
> >> Yeah, writing 0 is done with an intention to disable it but that’s not the
> >> way to
> >> have this option disabled. Infact there is no reason to write to it for
> >> DP1.4+ if sink
>
I tried a bit if I can break something with ccs but it seemed everything
work as expected with this fix.
Reviewed-by: Juha-Pekka Heikkila
On 4.12.2023 22.24, Ville Syrjala wrote:
From: Ville Syrjälä
plane_view_scanout_stride() currently assumes that we had to pad the
mapping stride with dum
On Tue, Dec 05, 2023 at 02:15:45PM +0200, Jani Nikula wrote:
> Reduce the duplication.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 24 ++--
> 1 file changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/
On Tue, 05 Dec 2023, "Shankar, Uma" wrote:
>> Yeah, writing 0 is done with an intention to disable it but that’s not the
>> way to
>> have this option disabled. Infact there is no reason to write to it for
>> DP1.4+ if sink
>> is compliant.
>
> The change looks ok and aligns with spec, its
> Rev
Reduce the duplication.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 9149dbd5..860
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, December 4, 2023 10:23 PM
> To: Nikula, Jani ; Ville Syrjälä
>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SE
On 05/12/2023 10:44, Nirmoy Das wrote:
Hi Tvrtko,
On 12/5/2023 11:05 AM, Tvrtko Ursulin wrote:
On 05/12/2023 08:50, Nirmoy Das wrote:
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
R
Hi Tvrtko,
On 12/5/2023 11:05 AM, Tvrtko Ursulin wrote:
On 05/12/2023 08:50, Nirmoy Das wrote:
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases
On Mon, Dec 04, 2023 at 10:24:43PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> plane_view_scanout_stride() currently assumes that we had to pad the
> mapping stride with dummy pages in order to align it. But that is not
> the case if the original fb stride exceeds the aligned stride use
On 05/12/2023 08:50, Nirmoy Das wrote:
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the c
On Mon, 2023-12-04 at 14:49 +0100, Maarten Lankhorst wrote:
> Works better for xe like that. obj is no longer const.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(
Enable Force Dispatch Ends Collection for DG2.
BSpec: 46001
Signed-off-by: Haridhar Kalvala
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/dri
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the caller of gen8_engine_reset_prepare() decid
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the caller of gen8_engine_reset_prepare() decide if a
failure in gen8_engine_reset_prepare is an error
On 30.11.2023 17:16, Paz Zcharya wrote:
There was an assumption that for iGPU there should be a 1:1 mapping
of GGTT to physical address pointing to actual framebuffer.
This assumption is not valid anymore for MTL.
Fix that by checking GGTT to determine the phys address.
The following algorith
On 01.12.2023 16:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the caller of gen8_engine_reset_prepare() decide if a
failure in gen8_engine_reset_prepare is an error
From: Ville Syrjälä
plane_view_scanout_stride() currently assumes that we had to pad the
mapping stride with dummy pages in order to align it. But that is not
the case if the original fb stride exceeds the aligned stride used
to populate the remapped view, which is calculated from the user
specif
Hi Nirmoy,
On Fri, Dec 01, 2023 at 04:44:43PM +0100, Nirmoy Das wrote:
> gen8_engine_reset_prepare() can fail when HW fails to set
> RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
> error as driver will retry.
>
> Let the caller of gen8_engine_reset_prepare() decide if a
> failure
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, December 4, 2023 10:18 PM
> To: Shankar, Uma ; Ville Syrjälä
>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET
> when using ra
On Mon, 04 Dec 2023, "Shankar, Uma" wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Monday, December 4, 2023 3:28 PM
>> To: Ville Syrjälä
>> Cc: intel-gfx@lists.freedesktop.org
>> Subject:
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Monday, December 4, 2023 3:28 PM
> To: Ville Syrjälä
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET
> when usin
Updated i915 hwmon with fixes for issues reported by static analysis tool.
Fixed integer overflow with upcasting.
v2:
- Added Fixes tag (Badal).
- Updated commit message as per review comments (Anshuman).
Fixes: 4c2572fe0ae7 ("drm/i915/hwmon: Expose power1_max_interval")
Reviewed-by: Badal Nilawa
Quoting Gustavo Sousa (2023-12-04 11:04:20-03:00)
>Quoting Matt Roper (2023-12-01 20:07:48-03:00)
>>On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
>>> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
>>> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
>>>
Quoting Matt Roper (2023-12-01 20:07:48-03:00)
>On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
>> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
>> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
>> > > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, December 4, 2023 3:28 PM
> To: Ville Syrjälä
> Cc: intel-gfx@lists.freedesktop.org; Manna, Animesh
>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to
> DP_LINK_BW_SET when using ra
On Fri, Dec 01, 2023 at 05:11:30PM +0100, Hans de Goede wrote:
> soc_gpio_set_value() already uses devm_gpiod_get(), lets be consistent
> and use devm_gpiod_get() for all GPIOs.
>
> This allows removing the intel_dsi_vbt_gpio_cleanup() function,
> which only function was to put the GPIO-descriptor
Works better for xe like that. obj is no longer const.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_cursor.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_curs
On Fri, 01 Dec 2023, Ville Syrjälä wrote:
> On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
>> The eDP 1.5 spec adds a clarification for eDP 1.4x:
>>
>> > For eDP v1.4x, if the Source device chooses the Main-Link rate by way
>> > of DPCD 00100h, the Sink device shall ignore DPCD 0011
On Fri, 01 Dec 2023, Hans de Goede wrote:
> soc_gpio_set_value() already uses devm_gpiod_get(), lets be consistent
> and use devm_gpiod_get() for all GPIOs.
>
> This allows removing the intel_dsi_vbt_gpio_cleanup() function,
> which only function was to put the GPIO-descriptors.
>
> Signed-off-by:
> -Original Message-
> From: Poosa, Karthik
> Sent: Friday, December 1, 2023 8:05 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Nilawar, Badal
> ; Poosa, Karthik
> Subject: [PATCH] drm/i915/hwmon: Fix issues found by static analysis tool in
> i915 hwmon
Keep the subj
On Fri, Dec 01, 2023 at 02:41:33PM +0530, Melanie Lobo wrote:
> Supports FP16 format which is a binary floating-point computer
> number format that occupies 16 bits in computer memory.Platform shall
> render compression in display engine to receive FP16 compressed formats.
The explanation here is
On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > > The cdclk tables were introduc
soc_gpio_set_value() already uses devm_gpiod_get(), lets be consistent
and use devm_gpiod_get() for all GPIOs.
This allows removing the intel_dsi_vbt_gpio_cleanup() function,
which only function was to put the GPIO-descriptors.
Signed-off-by: Hans de Goede
---
Note this applies on top of Andy's
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the caller of gen8_engine_reset_prepare() decide if a
failure in gen8_engine_reset_prepare is an error or not.
Cc: Tvrtko Ursulin
Cc: John Harri
On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
> The eDP 1.5 spec adds a clarification for eDP 1.4x:
>
> > For eDP v1.4x, if the Source device chooses the Main-Link rate by way
> > of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
>
> We write 0 to DP_LINK_BW_SET (DPCD
Updated i915 hwmon with fixes for issues reported by static analysis tool.
Fixed unintentional buffer overflow (OVERFLOW_BEFORE_WIDEN) with upcasting.
Fixes: 4c2572fe0ae7 ("drm/i915/hwmon: Expose power1_max_interval")
Signed-off-by: Karthik Poosa
---
drivers/gpu/drm/i915/i915_hwmon.c | 4 ++--
1
Hi Karthik,
On 01-12-2023 10:28, Karthik Poosa wrote:
Updated i915 hwmon with fixes for issues reported by static analysis tool.
Fixed unintentional buffer overflow (OVERFLOW_BEFORE_WIDEN) with upcasting.
v2: Updated commit message with details of issue [Jani].
Please add fixes tag.
Fixes: 4c2
The eDP 1.5 spec adds a clarification for eDP 1.4x:
> For eDP v1.4x, if the Source device chooses the Main-Link rate by way
> of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as i
> -Original Message-
> From: Poosa, Karthik
> Sent: Friday, December 1, 2023 10:28 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Nilawar, Badal
> ; Poosa, Karthik
> Subject: [PATCH] drm/i915/hwmon: Fix static analysis tool errors in i915
> hwmon
>
> Updated i915 hwm
Supports FP16 format which is a binary floating-point computer
number format that occupies 16 bits in computer memory.Platform shall
render compression in display engine to receive FP16 compressed formats.
This kernel change was tested with IGT patch,
https://patchwork.freedesktop.org/patch/562014
Updated i915 hwmon with fixes for issues reported by static analysis tool.
Fixed unintentional buffer overflow (OVERFLOW_BEFORE_WIDEN) with upcasting.
v2: Updated commit message with details of issue [Jani].
Signed-off-by: Karthik Poosa
---
drivers/gpu/drm/i915/i915_hwmon.c | 4 ++--
1 file cha
On Tue, Nov 28, 2023 at 12:12:08PM +0100, Andrzej Hajda wrote:
> On 28.11.2023 04:47, Paz Zcharya wrote:
> >
> > On Mon, Nov 27, 2023 at 8:20 PM Paz Zcharya wrote:
> > >
> > > On 21.11.2023 13:06, Andrzej Hajda wrote:
> > >
> > > > The simplest approach would be then do the same as in case of D
There was an assumption that for iGPU there should be a 1:1 mapping
of GGTT to physical address pointing to actual framebuffer.
This assumption is not valid anymore for MTL.
Fix that by checking GGTT to determine the phys address.
The following algorithm for phys_base should be valid for all platf
Hi Andrzej,
On Fri, Nov 24, 2023 at 08:53:04AM +0100, Andrzej Hajda wrote:
> Cursor size reduction is not supported since MTL.
>
> Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Thanks,
Andi
On Tue, Nov 28, 2023 at 08:03:31AM -0800, Matt Roper wrote:
> On Tue, Nov 28, 2023 at 03:54:51PM +0530, Balasubramani Vivekanandan wrote:
> > WAs 14011508470, 14011503030 were applied on IP versions beyond which
> > they are applicable. Fixed the IP version checks for these workarounds.
> >
> > Si
With TBT-ALT mode we are not programming C20 chip PLL's and
hence we don't need to check state verification. We don't
need to program DP link signal levels i.e.pre-emphasis and
voltage swing either.
This patch fixes dmesg errors like this one
"[drm] ERROR PHY F Write 0c06 failed after 3 retries."
On Wed, 29 Nov 2023, Karthik Poosa wrote:
> Updated i915 hwmon with fixes for issues reported by static analysis tool.
What's the problem? It's not enough to say this fixes a static analyzer
report. Tell us what the problem is, and why this is the fix.
BR,
Jani.
>
> Signed-off-by: Karthik Poos
Updated i915 hwmon with fixes for issues reported by static analysis tool.
Signed-off-by: Karthik Poosa
---
drivers/gpu/drm/i915/i915_hwmon.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwmon.c
index 975da
Never block for outstanding work on userptr object upon receipt of a
mmu-notifier. The reason we originally did so was to immediately unbind
the userptr and unpin its pages, but since that has been dropped in
commit b4b9731b02c3c ("drm/i915: Simplify userptr locking"), we never
return the pages to
On Tue, Nov 28, 2023 at 03:54:51PM +0530, Balasubramani Vivekanandan wrote:
> WAs 14011508470, 14011503030 were applied on IP versions beyond which
> they are applicable. Fixed the IP version checks for these workarounds.
>
> Signed-off-by: Balasubramani Vivekanandan
>
Reviewed-by: Matt Roper
Quoting Balasubramani Vivekanandan (2023-11-28 07:24:51-03:00)
>WAs 14011508470, 14011503030 were applied on IP versions beyond which
>they are applicable. Fixed the IP version checks for these workarounds.
>
>Signed-off-by: Balasubramani Vivekanandan
>
>---
> drivers/gpu/drm/i915/display/intel_di
On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > > The cdclk tables were introduc
After i915_active_unlock_wait i915_active can be still non-idle due
to barrier async handling in signal_irq_work. As a result one can observe
following errors:
bcs0: heartbeat pulse did not flush idle tasks
*ERROR* pulse active pulse_active [i915]:pulse_retire [i915]
*ERROR* pulsecount: 0
*ERRO
On Tue, Nov 28, 2023 at 12:12:08PM +0100, Andrzej Hajda wrote:
> On 28.11.2023 04:47, Paz Zcharya wrote:
> >
> > On Mon, Nov 27, 2023 at 8:20 PM Paz Zcharya wrote:
> >
> > Hey Andrzej,
> >
> > On a second thought, what do you think about something like
> >
> > + gen8_pte_t __iome
> -Original Message-
> From: Sousa, Gustavo
> Sent: Monday, November 27, 2023 8:33 PM
> To: Jani Nikula ; Kahola, Mika
> ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Skip state verification
> with TBT-ALT mode
>
> Q
On 28.11.2023 04:47, Paz Zcharya wrote:
On Mon, Nov 27, 2023 at 8:20 PM Paz Zcharya wrote:
On 21.11.2023 13:06, Andrzej Hajda wrote:
On 18.11.2023 00:01, Paz Zcharya wrote:
On Tue, Nov 14, 2023 at 10:13:59PM -0500, Rodrigo Vivi wrote:
On Sun, Nov 05, 2023 at 05:27:03PM +, Paz Zcharya w
> -Original Message-
> From: Sousa, Gustavo
> Sent: Monday, November 27, 2023 8:18 PM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Skip state verification
> with TBT-ALT mode
>
> Quoting Mika Kahola (2
WAs 14011508470, 14011503030 were applied on IP versions beyond which
they are applicable. Fixed the IP version checks for these workarounds.
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(
On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > > Use literal representatio
On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > > Use literal representatio
On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > > Use literal representatio
On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > Use literal representation of cdclk tables"). It has been almost 4 years
> > and the divider fie
On Mon, Nov 27, 2023 at 8:20 PM Paz Zcharya wrote:
>
> On 21.11.2023 13:06, Andrzej Hajda wrote:
> > On 18.11.2023 00:01, Paz Zcharya wrote:
> > > On Tue, Nov 14, 2023 at 10:13:59PM -0500, Rodrigo Vivi wrote:
> > > > On Sun, Nov 05, 2023 at 05:27:03PM +, Paz Zcharya wrote:
> > >
> > > Hi Rod
On Wed, Nov 22, 2023 at 02:26:55PM +0100, Andrzej Hajda wrote:
>
>
> On 21.11.2023 13:06, Andrzej Hajda wrote:
> > On 18.11.2023 00:01, Paz Zcharya wrote:
> > > On Tue, Nov 14, 2023 at 10:13:59PM -0500, Rodrigo Vivi wrote:
> > > > On Sun, Nov 05, 2023 at 05:27:03PM +, Paz Zcharya wrote:
> > >
Quoting Matt Roper (2023-11-27 16:00:44-03:00)
>This workaround has been dropped from all DG2 variants in the latest
>workaround database update.
>
>Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
> 1 file changed, 8 deletions
This workaround has been dropped from all DG2 variants in the latest
workaround database update.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i91
Quoting Jani Nikula (2023-11-27 13:47:22-03:00)
>On Mon, 27 Nov 2023, Mika Kahola wrote:
>> With TBT-ALT mode we are not programming C20 chip PLL's and
>> hence we don't need to check state verification. We don't
>> need to program DP link signal levels i.e.pre-emphasis and
>> voltage swing either
Quoting Mika Kahola (2023-11-27 12:47:02-03:00)
>With TBT-ALT mode we are not programming C20 chip PLL's and
>hence we don't need to check state verification. We don't
>need to program DP link signal levels i.e.pre-emphasis and
>voltage swing either.
>
>This patch fixes dmesg errors like this one
>
On Mon, 27 Nov 2023, Mika Kahola wrote:
> With TBT-ALT mode we are not programming C20 chip PLL's and
> hence we don't need to check state verification. We don't
> need to program DP link signal levels i.e.pre-emphasis and
> voltage swing either.
>
> This patch fixes dmesg errors like this one
>
>
On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> Use literal representation of cdclk tables"). It has been almost 4 years
> and the divider field was not really used yet. Let's remove it.
I think we need to go
With TBT-ALT mode we are not programming C20 chip PLL's and
hence we don't need to check state verification. We don't
need to program DP link signal levels i.e.pre-emphasis and
voltage swing either.
This patch fixes dmesg errors like this one
"[drm] ERROR PHY F Write 0c06 failed after 3 retries."
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