[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

2020-02-11 Thread Anusha Srivatsa
Disable Early Read and Src Swap (bit 14) by setting the chicken register. BSpec: 46045,52890 v2: Follow the Bspec implementation for the WA. v3: Have 2 separate defines for bit 14 and 15. - Rename register definitions with TGL_ prefix v4: Bspec changed. Again. Add WA to rcs_ WA list. Cc: Daniele

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

2020-02-07 Thread Matt Atwood
On Fri, Jan 31, 2020 at 03:17:05PM -0800, Anusha Srivatsa wrote: > Disable Early Read and Src Swap (bit 14) by setting the chicken > register. > > BSpec: 46045,52890 > > v2: Follow the Bspec implementation for the WA. > v3: Have 2 separate defines for bit 14 and 15. > - Rename register definition

[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

2020-01-31 Thread Anusha Srivatsa
Disable Early Read and Src Swap (bit 14) by setting the chicken register. BSpec: 46045,52890 v2: Follow the Bspec implementation for the WA. v3: Have 2 separate defines for bit 14 and 15. - Rename register definitions with TGL_ prefix v4: Bspec changed. Again. Add WA to rcs_ WA list. Cc: Daniele

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

2020-01-30 Thread Srivatsa, Anusha
> -Original Message- > From: Roper, Matthew D > Sent: Thursday, January 30, 2020 12:43 PM > To: Srivatsa, Anusha > Cc: intel-gfx@lists.freedesktop.org; Ceraolo Spurio, Daniele > > Subject: Re: [PATCH] drm/i915/tgl: Implement Wa_1606931601 > > On Wed, Jan 29, 2020 at 02:42:06PM -0800,

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

2020-01-30 Thread Matt Roper
On Wed, Jan 29, 2020 at 02:42:06PM -0800, Anusha Srivatsa wrote: > Disable Inter and intra Read Suppression (bit 15) and > Early Read and Src Swap (bit 14) by setting the chicken > register. > > BSpec: 46045,52890 > > v2: Follow the Bspec implementation for the WA. > v3: Have 2 separate defines f

[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

2020-01-29 Thread Anusha Srivatsa
Disable Inter and intra Read Suppression (bit 15) and Early Read and Src Swap (bit 14) by setting the chicken register. BSpec: 46045,52890 v2: Follow the Bspec implementation for the WA. v3: Have 2 separate defines for bit 14 and 15. - Rename register definitions with TGL_ prefix Cc: Matt Roper

[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

2020-01-24 Thread Anusha Srivatsa
Disable Early Read and Src Swap by setting the bit 14 and 15 in the chicken register. BSpec: 46045,52890 v2: Follow the Bspec implementation for the WA. Cc: Matt Roper Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + drivers/gpu/drm/i915/i915_reg.h

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

2020-01-24 Thread Srivatsa, Anusha
> -Original Message- > From: Roper, Matthew D > Sent: Thursday, January 23, 2020 9:50 AM > To: Srivatsa, Anusha > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 > > On Wed, Jan 22, 2020 at 03:40:27P

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

2020-01-23 Thread Matt Roper
On Wed, Jan 22, 2020 at 03:40:27PM -0800, Anusha Srivatsa wrote: > Disable Early Read and Src Swap by setting the bit 14 > and 15 in the chicken register. > > BSpec: 46045,52890 > HSDES: 1606931601 Hmm. The bspec WA description (which is very poorly written) only mentions setting bit 14, but com

[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

2020-01-22 Thread Anusha Srivatsa
Disable Early Read and Src Swap by setting the bit 14 and 15 in the chicken register. BSpec: 46045,52890 HSDES: 1606931601 Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 6 insertions(+