On Thu, Feb 04, 2016 at 06:11:28PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 04, 2016 at 10:43:21AM -0500, Lyude wrote:
> > We accidentally point both cfgcr registers for the second shared DPLL to
> > the same location in i915_reg.h. This results in a lot of hw pipe state
> > mismatches whenever we
On Thu, Feb 04, 2016 at 10:43:21AM -0500, Lyude wrote:
> We accidentally point both cfgcr registers for the second shared DPLL to
> the same location in i915_reg.h. This results in a lot of hw pipe state
> mismatches whenever we try to do a modeset that requires allocating the
> DPLL to a CRTC:
>
We accidentally point both cfgcr registers for the second shared DPLL to
the same location in i915_reg.h. This results in a lot of hw pipe state
mismatches whenever we try to do a modeset that requires allocating the
DPLL to a CRTC:
[drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_h
