On Thu, Apr 02, 2015 at 11:02:44AM +0530, Sonika Jindal wrote:
> We make use of HW tracking for Selective update region and enable frame sync
> on
> sink. We use hardware's hardcoded data values for frame sync and GTC.
>
> v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6095
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 270/270
We make use of HW tracking for Selective update region and enable frame sync on
sink. We use hardware's hardcoded data values for frame sync and GTC.
v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to
i915_psr
struct, add aux_frame_sync to independently control aux frame syn
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6095
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 270/270
On Tue, Mar 31, 2015 at 11:28:33AM +0530, Sonika Jindal wrote:
> We make use of HW tracking for Selective update region and enable frame sync
> on
> sink. We use hardware's hardcoded data values for frame sync and GTC.
>
> v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to
>-Original Message-
>From: Jindal, Sonika
>Sent: Tuesday, March 31, 2015 11:29 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Jindal, Sonika; R, Durgadoss; Vivi, Rodrigo
>Subject: [PATCH] drm/i915/skl: Enabling PSR2 SU with frame sync
>
>We make use of HW tracking for Selective update region
We make use of HW tracking for Selective update region and enable frame sync on
sink. We use hardware's hardcoded data values for frame sync and GTC.
v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to
i915_psr
struct, add aux_frame_sync to independently control aux frame syn
/skl: Enabling PSR2 SU with frame sync
We make use of HW tracking for Selective update region and enable frame sync on
sink. We use hardware's hardcoded data values for frame sync and GTC.
v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to
i915_psr
struct, add aux_frame
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6057
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 276/276
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Sonika Jindal
>Sent: Thursday, March 26, 2015 1:57 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH] drm/i915/skl: Enabling PS
We make use of HW tracking for Selective update region and enable frame sync on
sink. We use hardware's hardcoded data values for frame sync and GTC.
v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to
i915_psr
struct, add aux_frame_sync to independently control aux frame syn
On Monday 23 March 2015 02:10 PM, Sivakumar Thulasimani wrote:
On 3/20/2015 11:27 AM, Sonika Jindal wrote:
+#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
+#define EDP_PSR2_TP2_TIME_500(0<<8)
+#define EDP_PSR2_TP2_TIME_100(1<<8)
+#define EDP_PSR2_TP2_TI
On Mon, 2015-03-23 at 10:14 +0100, Daniel Vetter wrote:
> On Fri, Mar 20, 2015 at 11:26:19PM +, Vivi, Rodrigo wrote:
> > Hi Sonika,
> >
> > on the previous email I forgot to tell that we also need to add
> > somewhere a check to avoid PSR for resolutions bigger than 3200x2000.
> >
> > Althoug
On Fri, Mar 20, 2015 at 11:26:19PM +, Vivi, Rodrigo wrote:
> Hi Sonika,
>
> on the previous email I forgot to tell that we also need to add
> somewhere a check to avoid PSR for resolutions bigger than 3200x2000.
>
> Although most of displays that we have that support psr are 3200x1800 it
> is
On Saturday 21 March 2015 04:56 AM, Vivi, Rodrigo wrote:
Hi Sonika,
on the previous email I forgot to tell that we also need to add
somewhere a check to avoid PSR for resolutions bigger than 3200x2000.
Yes, I will add that check before enabling PSR2.
Although most of displays that we have tha
On 3/20/2015 11:27 AM, Sonika Jindal wrote:
+#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
+#define EDP_PSR2_TP2_TIME_500(0<<8)
+#define EDP_PSR2_TP2_TIME_100(1<<8)
+#define EDP_PSR2_TP2_TIME_250(2<<8)
Better to make all values inline, 5
On Saturday 21 March 2015 02:50 AM, Vivi, Rodrigo wrote:
On Fri, 2015-03-20 at 11:27 +0530, Sonika Jindal wrote:
We make use of HW tracking for Selective update region and enable frame sync on
sink. We use hardware's hardcoded data values for frame sync and GTC.
Before enabling HW tracking for
Hi Sonika,
on the previous email I forgot to tell that we also need to add
somewhere a check to avoid PSR for resolutions bigger than 3200x2000.
Although most of displays that we have that support psr are 3200x1800 it
is better to think a way to protect now than later.
Thanks,
Rodrigo.
On Fri,
On Fri, 2015-03-20 at 11:27 +0530, Sonika Jindal wrote:
> We make use of HW tracking for Selective update region and enable frame sync
> on
> sink. We use hardware's hardcoded data values for frame sync and GTC.
Before enabling HW tracking for PSR2 I'd like to know if all known bad
cases of bad H
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6014
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 274/274
We make use of HW tracking for Selective update region and enable frame sync on
sink. We use hardware's hardcoded data values for frame sync and GTC.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/i915_reg.h | 14 ++
drivers/gpu/drm/i915/intel_dp.c | 16
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