On Fri, Apr 19, 2019 at 10:10:26AM +0300, Imre Deak wrote:
Fix the order of lane, port parameters passed to the register macro.
Note that this was already partly fixed by commit
37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters
order")
Fixes: 58106b7d816e1 ("drm/i915:
On Fri, Apr 19, 2019 at 07:29:05PM +0300, Souza, Jose wrote:
> On Fri, 2019-04-19 at 19:04 +0300, Imre Deak wrote:
> > On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote:
> > > On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote:
> > > > Fix the order of lane, port parameters passed to the
On Fri, 2019-04-19 at 19:04 +0300, Imre Deak wrote:
> On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote:
> > On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote:
> > > Fix the order of lane, port parameters passed to the register
> > > macro.
> > >
> > > Note that this was already partly
On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote:
> On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote:
> > Fix the order of lane, port parameters passed to the register macro.
> >
> > Note that this was already partly fixed by commit
> > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macr
On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote:
> Fix the order of lane, port parameters passed to the register macro.
>
> Note that this was already partly fixed by commit
> 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right
> parameters order")
>
> Fixes: 58106b7d816e1 ("drm/i
Fix the order of lane, port parameters passed to the register macro.
Note that this was already partly fixed by commit
37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters
order")
Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically consistent")
Cc: José Robert
