Re: [Intel-gfx] [PATCH] drm/i915/hsw: enable atomic in L3 for some steppings.

2015-01-06 Thread Francisco Jerez
Zhigang Gong writes: > On Mon, Jan 05, 2015 at 07:27:26PM +0200, Francisco Jerez wrote: >> Zhigang Gong writes: >> >> > On Mon, Jan 05, 2015 at 05:03:16AM +0200, Francisco Jerez wrote: >> >> Zhigang Gong writes: >> >> >> >> > According to bspec, ROW_CHICKEN3's bit 6 which is to disable >> >>

Re: [Intel-gfx] [PATCH] drm/i915/hsw: enable atomic in L3 for some steppings.

2015-01-06 Thread Zhigang Gong
On Mon, Jan 05, 2015 at 07:27:26PM +0200, Francisco Jerez wrote: > Zhigang Gong writes: > > > On Mon, Jan 05, 2015 at 05:03:16AM +0200, Francisco Jerez wrote: > >> Zhigang Gong writes: > >> > >> > According to bspec, ROW_CHICKEN3's bit 6 which is to disable > >> > move of cacheable global atomi

Re: [Intel-gfx] [PATCH] drm/i915/hsw: enable atomic in L3 for some steppings.

2015-01-05 Thread Francisco Jerez
Zhigang Gong writes: > On Mon, Jan 05, 2015 at 05:03:16AM +0200, Francisco Jerez wrote: >> Zhigang Gong writes: >> >> > According to bspec, ROW_CHICKEN3's bit 6 which is to disable >> > move of cacheable global atomics to L3 is needed for GT3 D >> > stepping. >> > >> > I enabled it and tested i

Re: [Intel-gfx] [PATCH] drm/i915/hsw: enable atomic in L3 for some steppings.

2015-01-04 Thread shuang . he
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform Delta drm-intel-nightly Series Applied PNV 363/364

Re: [Intel-gfx] [PATCH] drm/i915/hsw: enable atomic in L3 for some steppings.

2015-01-04 Thread Zhigang Gong
On Mon, Jan 05, 2015 at 05:03:16AM +0200, Francisco Jerez wrote: > Zhigang Gong writes: > > > According to bspec, ROW_CHICKEN3's bit 6 which is to disable > > move of cacheable global atomics to L3 is needed for GT3 D > > stepping. > > > > I enabled it and tested it with HSW GT2 D stepping and GT

Re: [Intel-gfx] [PATCH] drm/i915/hsw: enable atomic in L3 for some steppings.

2015-01-04 Thread Francisco Jerez
Zhigang Gong writes: > According to bspec, ROW_CHICKEN3's bit 6 which is to disable > move of cacheable global atomics to L3 is needed for GT3 D > stepping. > > I enabled it and tested it with HSW GT2 D stepping and GT3 E stepping. > The atomics works fine in beignet. And it could get more than 1

[Intel-gfx] [PATCH] drm/i915/hsw: enable atomic in L3 for some steppings.

2015-01-04 Thread Zhigang Gong
According to bspec, ROW_CHICKEN3's bit 6 which is to disable move of cacheable global atomics to L3 is needed for GT3 D stepping. I enabled it and tested it with HSW GT2 D stepping and GT3 E stepping. The atomics works fine in beignet. And it could get more than 10x performance improvement with so