Quoting Rafael Antognolli (2018-01-26 17:58:29)
> On Fri, Jan 26, 2018 at 09:55:58AM -0800, Rafael Antognolli wrote:
> > On Fri, Jan 26, 2018 at 08:23:13AM +, Chris Wilson wrote:
> > > Quoting Rafael Antognolli (2018-01-26 01:26:34)
> > > > Write a PIPE_CONTROL with CS stall followed by 14 dwor
On Fri, Jan 26, 2018 at 09:55:58AM -0800, Rafael Antognolli wrote:
> On Fri, Jan 26, 2018 at 08:23:13AM +, Chris Wilson wrote:
> > Quoting Rafael Antognolli (2018-01-26 01:26:34)
> > > Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
> > > indirect context wa bb.
> >
> > 14
On Fri, Jan 26, 2018 at 08:23:13AM +, Chris Wilson wrote:
> Quoting Rafael Antognolli (2018-01-26 01:26:34)
> > Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
> > indirect context wa bb.
>
> 14 MI_NOOPS following? That isn't what you wrote in the code, but the
Agreed, so
Quoting Rafael Antognolli (2018-01-26 01:26:34)
> Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
> indirect context wa bb.
14 MI_NOOPS following? That isn't what you wrote in the code, but the
main thing you haven't explained is why. A normal batch will already
have a flush i
Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
indirect context wa bb.
References: HSD#1939868
Signed-off-by: Rafael Antognolli
---
drivers/gpu/drm/i915/intel_lrc.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
