On ke, 2016-03-16 at 18:06 -0700, Dongwon Kim wrote:
> For BXT, description of polarities of PORT_PLL_REF_SEL
> has been reversed for newer Gen9LP steppings according to the
> recent update in Bspec. This bit now should be set for
> "Non-SSC" mode for all Gen9LP starting from B0 stepping.
>
> v2:
On Tue, Mar 22, 2016 at 02:10:47AM -0700, Deak, Imre wrote:
> On ke, 2016-03-16 at 18:06 -0700, Dongwon Kim wrote:
> > For BXT, description of polarities of PORT_PLL_REF_SEL
> > has been reversed for newer Gen9LP steppings according to the
> > recent update in Bspec. This bit now should be set for
On ke, 2016-03-16 at 18:06 -0700, Dongwon Kim wrote:
> For BXT, description of polarities of PORT_PLL_REF_SEL
> has been reversed for newer Gen9LP steppings according to the
> recent update in Bspec. This bit now should be set for
> "Non-SSC" mode for all Gen9LP starting from B0 stepping.
>
> v2:
For BXT, description of polarities of PORT_PLL_REF_SEL
has been reversed for newer Gen9LP steppings according to the
recent update in Bspec. This bit now should be set for
"Non-SSC" mode for all Gen9LP starting from B0 stepping.
v2: Only B0 and newer stepping should be affected by this
change.
Si
On Tue, 2016-03-15 at 16:37 -0700, Dongwon Kim wrote:
> For BXT, Polarity of PORT_PLL_REF_SEL is reversed in
> its description in Bspec. This bit should be set for
> "Non-SSC".
Thanks for the patch.
In the future please also mention where the change originates from, in
this case it is a recent up
For BXT, Polarity of PORT_PLL_REF_SEL is reversed in
its description in Bspec. This bit should be set for
"Non-SSC".
Signed-off-by: Dongwon Kim
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/d
