On Mon, Nov 11, 2013 at 02:46:28PM -0800, Ben Widawsky wrote:
> The pipe B and pipe C interrupt mask and enable registers are now part
> of the pipe, so disabling the pipe power wells will lost the contests of
> the registers.
>
> Art totally debugged this one!
>
> v2: Use the irq_lock to clarify
The pipe B and pipe C interrupt mask and enable registers are now part
of the pipe, so disabling the pipe power wells will lost the contests of
the registers.
Art totally debugged this one!
v2: Use the irq_lock to clarify code, and prevent future bugs (Daniel)
Cc: Art Runyan
Cc: Paulo Zanoni
S
On Sat, Nov 9, 2013 at 6:20 PM, Ben Widawsky wrote:
> On Sat, Nov 09, 2013 at 10:13:21AM +0100, Daniel Vetter wrote:
>> On Fri, Nov 08, 2013 at 02:29:46PM -0800, Ben Widawsky wrote:
>> > The pipe B and pipe C interrupt mask and enable registers are now part
>> > of the pipe, so disabling the pipe
On Sat, Nov 09, 2013 at 10:13:21AM +0100, Daniel Vetter wrote:
> On Fri, Nov 08, 2013 at 02:29:46PM -0800, Ben Widawsky wrote:
> > The pipe B and pipe C interrupt mask and enable registers are now part
> > of the pipe, so disabling the pipe power wells will lost the contests of
> > the registers.
>
On Fri, Nov 08, 2013 at 02:29:46PM -0800, Ben Widawsky wrote:
> The pipe B and pipe C interrupt mask and enable registers are now part
> of the pipe, so disabling the pipe power wells will lost the contests of
> the registers.
>
> Art totally debugged this one!
>
> Cc: Art Runyan
> Cc: Paulo Zan
The pipe B and pipe C interrupt mask and enable registers are now part
of the pipe, so disabling the pipe power wells will lost the contests of
the registers.
Art totally debugged this one!
Cc: Art Runyan
Cc: Paulo Zanoni
Signed-off-by: Ben Widawsky
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drivers/gpu/drm/i915/intel_pm.c | 12 ++
