On Thu, Nov 14, 2013 at 07:15:52PM +0100, Thomas Richter wrote:
> On 14.11.2013 09:21, Daniel Vetter wrote:
>
> >On gen2/3 the fence registers make a tile range look linear to both
> >the gpu and the cpu. On gen4+ the fence registers are only for access
> >with the cpu, and everything else needs t
On 14.11.2013 09:21, Daniel Vetter wrote:
On gen2/3 the fence registers make a tile range look linear to both
the gpu and the cpu. On gen4+ the fence registers are only for access
with the cpu, and everything else needs to take tiling into account
explicitly (and there are bits in the registers
On Thu, Nov 14, 2013 at 8:14 AM, Thomas Richter wrote:
> Are you *really sure* GEN2 does have tiling? Or could it be that this bit is
> used for something else and probably turns on some weird powersaving feature
> that creates some mischief with the FIFO? After all, a tile cannot always be
> 128
On 13.11.2013 21:20, Daniel Vetter wrote:
Thanks Daniel for your explanations. As always, very helpful.
Tile buffers aren't linear any more in memory. Tiles are 2kb in size and
are laid out in x-major direction. The tile itself is 128 bytes wide and
16 lines high. So presuming you start scann
On Wed, Nov 13, 2013 at 08:50:50PM +0100, Thomas Richter wrote:
> On 12.11.2013 18:22, Daniel Vetter wrote:
>
> Thanks for the explanation how the fifos work, that was helpful.
>
>
> >Yeah, I've meant BEND = max and AEND split so that the two resulting sizes
> >are proportional to the pixel cloc
On 12.11.2013 18:22, Daniel Vetter wrote:
Thanks for the explanation how the fifos work, that was helpful.
Yeah, I've meant BEND = max and AEND split so that the two resulting sizes
are proportional to the pixel clock (i.e. both pipes should take equal
amount of time roughly to go through the
On Tue, Nov 12, 2013 at 05:41:12PM +0100, Thomas Richter wrote:
> Am 11.11.2013 16:43, schrieb Daniel Vetter:
> >Oh, that's really interesting. gen2 has a unified display fifo on
> >machines that support 2 outputs. DSPARB tells the hw how to exactly
> >split this up between the two pipes. There are
Am 11.11.2013 16:43, schrieb Daniel Vetter:
Oh, that's really interesting. gen2 has a unified display fifo on
machines that support 2 outputs. DSPARB tells the hw how to exactly
split this up between the two pipes. There are two bit ranges of
interest here:
/* snip */
Hmm, why I understand *th
On Mon, Nov 11, 2013 at 4:33 PM, Thomas Richter wrote:
> Now, how much is known about the register DSPARB, found at offset 0x70030?
>
> Because, if I just feed this register with "correct" values (for whatever
> "correct" means), I do get a stable image
> on pipe A and pipe B. I haven't found out
Am 08.11.2013 17:32, schrieb Daniel Vetter:
Kernel has a tool in scripts/checkpatch.pl which will tell you what's all
off ;-) Also sob line and similar essential things are missing, but the
script should notice this all.
Also I think it'd be good to extract this hack into a little helper
functio
Hi Daniel, dear intel-experts,
please find a revised patch attached that addresses the flicker with
panning on the i830 chipset. This patch has now been tested
on various screen layouts and seems to be quite reliable, i.e. I haven't
seen the flicker since.
Unfortunately, I have not been able
On Fri, Nov 08, 2013 at 04:25:01PM +0100, Thomas Richter wrote:
> Hi Daniel, dear intel-experts,
>
> please find a revised patch attached that addresses the flicker with
> panning on the i830 chipset. This patch has now been tested
> on various screen layouts and seems to be quite reliable, i.e. I
12 matches
Mail list logo
