Listen, here’s the problem I’m having guys and I need someone to reply back to
me. Because I wrote to FSF and they wrote me right back and I join their and I
have no problem with free software and complain but I don’t exactly know what
you want me to do and I don’t have “git” on my
Subject: [PATCH 0/1] Add PXP firmware respose on ARB failure
Add PXP firmware respose on ARB failure
Signed-off-by: Alan Previn
Alan Previn (1):
drm/i915/pxp: Add firmware status when ARB session fails
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_te
On Thu, 19 May 2022 at 10:55, Christian König
wrote:
>
> Just sending that out once more to intel-gfx to let the CI systems take
> a look.
If all went well it should normally appear at [1][2], if CI was able
to pick up the series.
Since it's not currently there, I assume it's temporarily stuck i
On Wed, Feb 26, 2020 at 03:56:36PM +0100, Linus Walleij wrote:
> On Wed, Feb 26, 2020 at 3:34 PM Ville Syrjälä
> wrote:
> > On Wed, Feb 26, 2020 at 01:08:06PM +0100, Linus Walleij wrote:
> > > On Wed, Feb 26, 2020 at 12:57 PM Ville Syrjälä
> > > wrote:
> > > > On Tue, Feb 25, 2020 at 10:52:25PM +
On Wed, Feb 26, 2020 at 3:34 PM Ville Syrjälä
wrote:
> On Wed, Feb 26, 2020 at 01:08:06PM +0100, Linus Walleij wrote:
> > On Wed, Feb 26, 2020 at 12:57 PM Ville Syrjälä
> > wrote:
> > > On Tue, Feb 25, 2020 at 10:52:25PM +0100, Linus Walleij wrote:
> >
> > > > I have long suspected that a whole b
On Wed, Feb 26, 2020 at 01:08:06PM +0100, Linus Walleij wrote:
> On Wed, Feb 26, 2020 at 12:57 PM Ville Syrjälä
> wrote:
> > On Tue, Feb 25, 2020 at 10:52:25PM +0100, Linus Walleij wrote:
>
> > > I have long suspected that a whole bunch of the "simple" displays
> > > are not simple but contains a
On Wed, Feb 26, 2020 at 12:57 PM Ville Syrjälä
wrote:
> On Tue, Feb 25, 2020 at 10:52:25PM +0100, Linus Walleij wrote:
> > I have long suspected that a whole bunch of the "simple" displays
> > are not simple but contains a display controller and memory.
> > That means that the speed over the link
Subject: Re: [PATCH 04/12] drm: Nuke mode->vrefresh
Message-ID: <20200226115708.gh13...@intel.com>
References: <20200219203544.31013-1-ville.syrj...@linux.intel.com>
<20200219203544.31013-5-ville.syrj...@linux.intel.com>
<0f278771-79ce-fe23-e72c-3935dbe82...@samsung.com>
<20200225112114.ga13.
Next try of prework for unpinned DMA-buf operation.
Only send to intel-gfx to trigger unit tests on the following patches.
Christian.
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Hi everyone,
I don't know if this is too specialised for this list. Anyway, no harm in
asking the question :-)
*Preamble*
Build: Yocto from the Apollo Lake BSP release *gold, *
Hardware: Oxbow Hill Rev B CRB with Intel Atom E3950 and 4GB DDR3 RAM (one
SODIMM)
Build: core-image-sato-sdk
Installed
On 11.11.2016 18:16, Daniel Vetter wrote:
> On Fri, Nov 11, 2016 at 07:41:10PM +0200, Abdiel Janulgue wrote:
>> A lot of igt testcases need some GPU workload to make sure a race
>> window is big enough. Unfortunately having a fixed amount of
>> workload leads to spurious test failures or overtly lo
On 17/06/15 12:04, Daniel Vetter wrote:
> On Fri, Jun 12, 2015 at 09:25:36PM +0100, Dave Gordon wrote:
>> Updated version split into two. The first tidies up the _ring_prepare()
>> functions and removes the corner case where we might have had to wait
>> twice; the second is a temporary workaround t
On Wed, 17 Jun 2015, Daniel Vetter wrote:
> On Fri, Jun 12, 2015 at 09:25:36PM +0100, Dave Gordon wrote:
>> Updated version split into two. The first tidies up the _ring_prepare()
>> functions and removes the corner case where we might have had to wait
>> twice; the second is a temporary workaroun
On Fri, Jun 12, 2015 at 09:25:36PM +0100, Dave Gordon wrote:
> Updated version split into two. The first tidies up the _ring_prepare()
> functions and removes the corner case where we might have had to wait
> twice; the second is a temporary workaround to solve a kernel OOPS that
> can occur if log
Updated version split into two. The first tidies up the _ring_prepare()
functions and removes the corner case where we might have had to wait
twice; the second is a temporary workaround to solve a kernel OOPS that
can occur if logical_ring_begin is called while the ringbuffer is not
mapped because
This series is revised based on Jani's good comments.
In this series the patch which read out DP link training
parameters from VBT is discarded as based on the comments
that I received.
Files changed:
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h
__
Addresses the comments and feedback herein. VLV2 and gen4 have separate bit
definitions now. The correct bits are selected in gen4x_dp_detect() based on
the detected platform.
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On Mon, Dec 30, 2013 at 07:59:49AM +0530, Oravil Nair wrote:
> Hi,
>
> i915_gem_object_pin(), during i915 driver create, seems to write to the
> memory written by BIOS. Where can the start address be specified to
> allocate memory so that the memory written by BIOS is not overwritten at
> initiali
Hi,
i915_gem_object_pin(), during i915 driver create, seems to write to the
memory written by BIOS. Where can the start address be specified to
allocate memory so that the memory written by BIOS is not overwritten at
initialization?
Thanks
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On Mon, Aug 26, 2013 at 04:05:11PM +0300, Michael S. Tsirkin wrote:
> On Wed, Aug 21, 2013 at 11:22:58AM +0200, Sedat Dilek wrote:
> > [ Re: [Intel-gfx] i915 producing warnings with kernel 3.11-rc5 ]
> >
> > Hi,
> >
> > saw your posting in [1]... can you try the patches below?
> > Not sure if the
Hi all,
Two things:
- Please _always_ include a public mailing list when reporting bugs, your
dear maintainer sometimes slacks off.
- We need to see the error_state before we can assess what kind of hang you
have (it's like gettting a SIGSEGV for a normal program, no two gpu hangs
are the same ...
Hi,
This is the second verion of the clipping/interpolation patches.
Main differences:
- I tried to take all of Paul's remarks into account
- I exploded the first patch in 4 independant ones
- I've added a patch to ensure that integers pass through unscathed
Patch 4/9 is (slightly) controversi
There are many bugs open on fd.o regarding missing modes that are supported on
Windows and other closed source drivers.
>From EDID spec we can (might?) infer modes using GTF and CVT when monitor
>allows it trough range limited flag... obviously limiting by the range.
>From our code:
* EDID spec
There are many bugs open on fd.o regarding missing modes that are supported on
Windows and other closed source drivers.
>From EDID spec we can (might?) infer modes using GTF and CVT when monitor
>allows it trough range limited flag... obviously limiting by the range.
>From our code:
* EDID spec
http://www.signsandsites.com/wp-content/themes/duotone/nav21.php
Muhammad Jamil
Sumintar
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W0rking fr0m h0me Ieads t0 sh0cking m0ney resuIts!
http://jadehurtz.com/coffeemoney.php?apohgoto=64
Tue, 3 Apr 2012 13:42:09
__
" So Tom took his goods out himself, and soughtemployers for Bert who did not
know of this strain of poetry inhis nature" (c) britin wynton
_
GIT: [Intel-gfx] [PATCH 1/3] drm/i915: proper use of forcewake
GIT: [Intel-gfx] [PATCH 2/3] drm/i915: refcounts for forcewake
GIT: [Intel-gfx] [PATCH 3/3] drm/i915: userspace interface to the forcewake
refcount
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GIT: [Intel-gfx] [PATCH 1/4] drm/i915: proper use of forcewake
GIT: [Intel-gfx] [PATCH 2/4] drm/i915: refcounts for forcewake
GIT: [Intel-gfx] [PATCH 3/4] drm/i915: userspace interface to the forcewake
refcount
GIT: [Intel-gfx] [PATCH 4/4] drm/i915: optional fewer warning patch
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These are some prep patches I'd like to get feedback on. I've only
compile tested them so far (the actual hw support code this is for was
tested before the split), so testing would be appreciated as well.
Thanks,
Jesse
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Hi folks,
I am a bit new to graphics, but had a few questions that I was hoping that
someone could answer for me. I hope this is the right forum to ask these
questions.
My interest is in seeing whether I can use the Intel integrated graphics part
for non-graphics (GPGPU) work, while driving the
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