[Intel-gfx] [RFC 7/8] drm: Add support for pps and compression mode command packet

2015-08-12 Thread vikas . korjani
From: vkorjani After enabling DSC we need to send compression mode command packet and pps data packet, for which 2 new data types are added 07h Compression Mode Data Type Write , short write, 2 parameters 0Ah PPS Long Write (word count determines number of bytes) This patch adds support to send

[Intel-gfx] [RFC 3/8] drm/i915/bxt: Init PPS, Calculate DSI frequency and DPHY parameters for DSC

2015-08-12 Thread vikas . korjani
From: vkorjani This patch adds code to initialize Picture Parameter set (PPS) data structure for DSC. DSC is enabled than the bitrate should be calculated using the formula pixel_clock * bits_per_pixel / lane_count, where bits_per_pixel can be 8bpp, 10bpp, 12bpp. value of bits_per_pixel is avail

[Intel-gfx] [RFC 6/8] drm/i915/bxt: Enable/Disable DSC and programme PPS.

2015-08-12 Thread vikas . korjani
From: vkorjani Program the PPS data from intel_dsc->vesa_dsc_pps_data into display controller register DSCx_PICTURE_PARAMETER_SET_x. DSC should be enabled in MIPI Port control register, after programming PPS register Disable DSC in disable sequence after disabling port. Signed-off-by: vkorjani

[Intel-gfx] [RFC 8/8] drm/i915/bxt: Send PPS packet and compression mode command packet

2015-08-12 Thread vikas . korjani
From: vkorjani This patch adds code to send pps long packet and compression mode command packet. Signed-off-by: vkorjani --- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/

[Intel-gfx] [RFC 5/8] drm/i915/bxt: Program MIPI_DPI_RESOLUTION for DSC

2015-08-12 Thread vikas . korjani
From: vkorjani Program the MIPI_DPI_RESOLUTION register horizontal resolution using the byte_to_pixels() DSC specific function in case of compression enabled. For non-compressed video, the number of pixels in active region are computed as usual. Change-Id: Iacea79352fa67a40a1d305494539f7c99f2715

[Intel-gfx] [RFC 1/8] drm/915/bxt: Adding DSC VBT parameter and PPS structures

2015-08-12 Thread vikas . korjani
From: vkorjani Adding pps structure as per VESA DSC v1.1 spec. Adding "vbt_dsc_param" vbt structure to store DSC info vbt_dsc_param and pps structures are made part of intel_vbt_data. Signed-off-by: vkorjani Signed-off-by: Yogesh Mohan Marimuthu --- drivers/gpu/drm/i915/i915_drv.h |2 +

[Intel-gfx] [RFC 2/8] drm/i915/bxt: Adding registers to support DSC

2015-08-12 Thread vikas . korjani
From: vkorjani This patch adds register definitions required to support DSC feature. Signed-off-by: vkorjani Signed-off-by: Yogesh Mohan Marimuthu --- drivers/gpu/drm/i915/i915_reg.h | 126 + drivers/gpu/drm/i915/intel_bios.h |1 + 2 files changed, 1

[Intel-gfx] [RFC 4/8] drm/i915/bxt: MIPI DSI Register Programming for DSC

2015-08-12 Thread vikas . korjani
From: vkorjani For compression enabled, the number of bytes in active region cannot be calculated just by multiplying number of pixels and bits per pixel, formula in HLD is ceil((ceil(pixels/num_slice) * bpp) / 8) * num_slice hence modifying txbyteclkhs() to accommodate calculation for DSC Enab

[Intel-gfx] [RFC 0/8] *** DSC Inital Design RFC ***

2015-08-12 Thread vikas . korjani
From: vkorjani s RFC is for feature Display Stream Compression (DSC) for BXT, It is a VESA defined standard to compress and decompress image in display streams in a link independent manner. Some of the basic requirements of the standard are to support higher resolution on a given display link wit