d lead to unwanted side effects.
>*/
> - if (mode & EMIT_FLUSH)
> + if ((mode & EMIT_FLUSH) &&
> + !(IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))))
> bit_group_
lin
> Cc: Andrzej Hajda
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workaroun
that it will catch all possible error conditions. Use drm_warn instead.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Mika Kuoppala
> Cc: Jani Nikula
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 +++-
> 1 file changed, 3 insertions(+),
Tvrtko Ursulin writes:
> On 28/01/2022 22:10, Michael Cheng wrote:
>> Re-work invalidate_csb_entries to use drm_clflush_virt_range. This will
>> prevent compiler errors when building for non-x86 architectures.
>>
>> Signed-off-by: Michael Cheng
>> ---
>> drivers/gpu/drm/i915/gt/intel_execlist
the updated entry.
>
> Signed-off-by: Matthew Auld
> Cc: Mika Kuoppala
Makes sense to follow the same pattern as the other writes.
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drive
t register address. We only use this
>> > register in error state dumps so the mistake hasn't caused any real
>> > problems, but fixing it will hopefully make the error state dumps a bit
>> > more useful for debugging.
>> >
>> > Fixes: e50dbdbfd9fb (&
;
> Suggested-by: Daniel Vetter
> Signed-off-by: Matthew Auld
> Cc: Ville Syrjälä
> Cc: Mika Kuoppala
> ---
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 173 +-
> drivers/gpu/drm/i915/i915_drv.h | 9 -
> 2 files changed, 169 insertions(+), 13
Matthew Auld writes:
> Try to document the object caching related bits, like cache_coherent and
> cache_dirty.
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Matthew Auld
> ---
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 135 +-
> drivers/gpu/drm/i915/i915_drv.h
Rodrigo Vivi writes:
> On Thu, Jun 03, 2021 at 03:07:54PM -0700, Manasi Navare wrote:
>> Static analysis identified an issue in skl_crtc_allocate_ddb where
>> mbus_offset may be used uninitialized.
>> This patch fixes it.
>
> I'm sorry, but I really cannot see what this tool is seeing...
> I even
ot;drm/i915: Request watchdog infrastructure")
> Cc: Daniel Vetter
Reviewed-by: Mika Kuoppala
> ---
> Test-with: 20210318162400.2065097-1-tvrtko.ursu...@linux.intel.com
> ---
> drivers/gpu/drm/i915/i915_request.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Chris Wilson writes:
> Quoting Mika Kuoppala (2021-02-10 10:49:55)
>> Chris Wilson writes:
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
>> > b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> > index d34770ae4c9a..5ac9eb4a3a92 100644
>> > --- a/d
Chris Wilson writes:
> The surface_state_base is an offset into the batch, so we need to pass
> the correct batch address for STATE_BASE_ADDRESS.
>
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson
> Cc: Mika K
Chris Wilson writes:
> Periodically check, for example when idling and upon closing user
> contexts, whether or not some client has written into unallocated PTE in
> their ppGTT.
>
> Signed-off-by: Chris Wilson
> ---
> .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++--
> drivers/gpu/
Chris Wilson writes:
> The heartbeat runs through a few phases that we expect to complete
> within a certain number of heartbeat intervals. First we must submit the
> heartbeat to the queue, and if the queue is occupied it may take a
> couple of intervals before the heartbeat preempts the workloa
led.
> @@ -139,6 +146,8 @@ static void heartbeat(struct work_struct *wrk)
> "stopped heartbeat on %s",
> engine->name);
> }
> +
> + rq->emitted_jiffies = ji
Chris Wilson writes:
> Use the defaults we store on the engine when resetting the heartbeat as
> we may have had to adjust it from the config value during initialisation.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../gpu/drm/i915/gt/selftest_
Chris Wilson writes:
> Instead of copying the whole table to each category (mocs, l3cc), use a
> single table with a pointer to it if the category is enabled.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/se
Chris Wilson writes:
> The name very often may be freed independently of the fence, with the
> only protection being RCU. To be safe as we read the names, hold RCU.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_sw_fence.
Chris Wilson writes:
> As soon as we mark a request as completed, it may be retired. So when
> cancelling a request and marking it complete, make sure we first keep a
> reference to the request.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
gt; +static struct hwsp_semaphore hwsp_semaphore(struct intel_engine_cs *engine)
> +{
> + struct hwsp_semaphore s;
> +
> + s.va = memset32(engine->status_page.addr + 1000, 0, 1);
> + s.ggtt = (i915_ggtt_offset(engine->status_page.vma) +
> + offset_in_pa
Chris Wilson writes:
> Verify that context isolation is also preserved when accessing
> context-local registers with relative-mmio commands.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 88 ++
y: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> index f8c79
as part of a forced-preemption.
> In which case, do not waste time in suspending the request, capturing
> the error, and just cancel it instead.
>
> Testcase: igt/gem_ctx_persistence/many-contexts
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../drm/i91
read of the current request.
>
> Suggested-by: Mika Kuoppala
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 --
> 1 file changed, 2 deletions(-)
>
&g
Chris Wilson writes:
> Flush; invalidate; change registers; invalidate; flush.
>
> Will this finally work on every device? Or will Baytrail complain again?
>
> On the positive side, we immediate see the benefit of having hsw-gt1 in
> CU.
CI
Acked-by: Mika Kuoppala
>
y yell if we cant proceed.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 15 ++-
> 1 file changed, 2 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_sub
Chris Wilson writes:
> Before we clear any state that may be being written by an interrupt
> handler on another core, flush the interrupt handlers.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c
switching back to a
> completed context")
> References: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewinding")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 34 ++
Chris Wilson writes:
> Treat the dependency between bonded requests as weak and leave the
> remainder of the pair on the GPU if one hangs.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 ++
&g
stem running in the remote
> chance that they are able to extract the original debug logs.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/Kconfig.debug | 16
> drivers/gpu/drm/i915/i915_gem.h|
Chris Wilson writes:
> During the reset of ring submission, we first stop the engine by
> clearing the HEAD/TAIL and marking the ring as disabled. However, it
> would be safer to disable the ring (after emptying) before resetting the
> HEAD/TAIL.
>
> Suggested-by: Mika Kuoppal
.display.has_hotplug = 1,
> @@ -571,8 +573,7 @@ static const struct intel_device_info hsw_gt3_info = {
> .dma_mask_size = 39, \
> .ppgtt_type = INTEL_PPGTT_FULL, \
> .ppgtt_size = 48, \
> - .has_64bit_reloc = 1, \
> - .has_reset_engine = 1
Oh we alrea
Chris Wilson writes:
> Quoting Mika Kuoppala (2021-01-19 10:25:14)
>> Chris Wilson writes:
>>
>> > CI reports that Baytail requires one more invalidate after CACHE_MODE
>> > for it to be happy.
>> >
>> > Fixes: ace44e13e577 ("drm/i91
rt of resume as a guardian memory
> barrier.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../gpu/drm/i915/gt/intel_ring_submission.c | 93 +--
> 1 file changed, 42 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/d
e, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));
> +
Not related to this patch but this makes me wondering if the actual
disable should be at this point before zeroing as manipulating the
head again might kick the hardware forward.
As in this point the 'ring must be empty' is satis
Chris Wilson writes:
> The engine resets selftests kick the tasklets, safe up until now as only
> execlists supported engine resets.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 18 ++
Chris Wilson writes:
> CI reports that Baytail requires one more invalidate after CACHE_MODE
> for it to be happy.
>
> Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing
> residuals")
> Signed-off-by: Chris Wilson
> Cc: Mika Ku
64885766-722
> execlists_reset_csb.constprop 1587 777-810
> Total: Before=1605815, After=1605086, chg -0.05%
>
> Signed-off-by: Chris Wilson
> Cc: Jani Nikula
Reviewed-by: Mika Kuoppala
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 6
; <3> [616.860901] i915/intel_heartbeat_live_selftests: live_heartbeat_fast
> failed with error -22
>
> v2: More context from CI.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 1
Chris Wilson writes:
> Since we are system_highpri_wq, we expected the heartbeat to be
> scheduled promptly. However, we see delays of over 10ms upsetting our
> assertions. Accept this as inevitable and bump the error threshold to
> 20ms (from 6ms).
>
> Signed-off-by: Chris Wilson
> ---
> drive
Chris Wilson writes:
> Quoting Mika Kuoppala (2021-01-12 19:19:34)
>> Chris Wilson writes:
>>
>> > In our tests where we measure the elapsed time on both the CPU and CS
>> > using a udelay, our CS results match the udelay much more accurately
>
Chris Wilson writes:
> In our tests where we measure the elapsed time on both the CPU and CS
> using a udelay, our CS results match the udelay much more accurately
> than the ktime (even when using ktime_get_fast_ns). With preemption
> disabled, we can go one step lower than ktime and use local_c
Chris Wilson writes:
> Inject a fault into the engine reset and check that the outstanding
> requests are completed despite the failed reset.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 133 +++
> 1 file changed, 133 insertions(+)
>
> d
Chris Wilson writes:
> Since we process schedule-in of a context after submitting the request,
> if we decide to reset the context at that time, we also have to cancel
> the requets we have marked for submission.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
&
> - if (i915_request_has_waitboost(rq)) {
> - GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters));
> + if (test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags))
> atomic_dec(&rq->engine->gt->rps.
ot touch the shrinker.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i91
reedesktop.org/drm/intel/-/issues/2859
> Fixes: 5f4ae2704d59 ("drm/i915: Identify Cometlake platform")
> Signed-off-by: Chris Wilson
> Cc: # v5.9+
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
> 1 file changed, 1 insertion(
_engine.h"
>
> +#include "dma_resv_utils.h"
> #include "i915_gem_ioctls.h"
> #include "i915_gem_object.h"
>
> @@ -84,11 +85,8 @@ i915_gem_object_wait_reservation(struct dma_resv *resv,
>* Opportunistically prune the fences iff we
e first pass.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 22 ++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fenci
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 203 ++-
> 1 file changed, 202 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> b/drivers/gpu/drm/i915/gt/s
> - RUNTIME_INFO(ce->engine->i915)->cs_timestamp_period_ns;
> + const u32 period = ce->engine->gt->clock_period_ns;
>
> return mul_u32_u32(ewma_runtime_read(&ce->runtime.avg), period);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
Chris Wilson writes:
> Reduce the pollution of intel_engine.h by moving gen8_emit_pipe_control
> and friends to gen8_engine_cs.h
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/display/intel_overlay.c | 1 +
> dri
garbage. Since this doesn't always happen,
> + * let's poison such state so that we more quickly spot when
> + * we falsely assume it has been preserved.
> + */
> + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> + memset(engine-&g
Chris Wilson writes:
> The workarounds are tied to the GT and we should derive the tests local
> to the GT.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../gpu/drm/i915/gt/selftest_workarounds.c| 189 --
> 1 file changed,
Chris Wilson writes:
> When we reset the legacy ring context, due to potential corruption over
> suspend/resume, remove the valid bit so that we avoid loading garbage.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_rin
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-12-10 10:36:07)
>> Chris Wilson writes:
>>
>> > Some rcs0 workarounds were being incorrectly applied to the GT, and so
>> > we failed to restore the expected register settings after a reset.
>
Chris Wilson writes:
> Some rcs0 workarounds were being incorrectly applied to the GT, and so
> we failed to restore the expected register settings after a reset.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 67 ++---
> 1 file changed, 33
Chris Wilson writes:
> Concurrent access to a mmap is covered by gem_mmap_gtt/concurrent,
> if we add tiled access to it, we make gem_threaded_access_tiled entirely
> redundant.
Aww, my first ever test for igt iirc.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Chris Wilson writes:
> Now that the only user of the uninterruptible wait was eliminated,
> remove the support.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_gt_requests.c | 7 +--
> 1 file changed, 1 inse
dates do not prevent
> the faults. So far the only effect has been from inducing a delay
> between reuse of the iommu on the GPU.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Acked-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 11 ++-
>
f-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 25 ++---
> 1 file changed, 10 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c5
rce preemption")
> Signed-off-by: Chris Wilson
> Cc: # v5.5+
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/
ht
> requests")
> Signed-off-by: Chris Wilson
> Cc: # v5.7+
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel
Chris Wilson writes:
> The GT and engine reset failures are completely invisible when looking at
> a trace for a bug, but are vital to understanding the incomplete flow.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/
gned-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7f25894e41d5..0c7f1e3dee5c
Chris Wilson writes:
> The old IPS interface did not match the RPS interface that we tried to
> plug it into (bool vs int return). Once repaired, our minimal
> selftesting is finally happy!
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> dr
Reported-by: Hulk Robot
> Signed-off-by: Zhang Xiaoxu
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/selftests/i915_request.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
> b/drivers/gpu/
> Signed-off-by: Zhang Xiaoxu
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/selftests/i915_request.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
> b/drivers/gpu/drm/i915/selftests/i915_
atic void print_request(struct drm_printer *m,
> rq->fence.context, rq->fence.seqno,
> i915_request_completed(rq) ? "!" :
> i915_request_started(rq) ? "*" :
> +!i915_sw_fence_signa
e issue from being reproduced, we can presume the post-sync op is not
> so post-sync.
>
Only thing that is mildly surpricing is that first one doesnt
need postop write.
> Testcase: igt/gem_exec_fence/parallel
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: sta...@vger
32 flags0, u32 flags1)
Opportunity to swap the offset/value to be in line with the actual qw
write. Just an observation rather than a value add proposal.
Reviewed-by: Mika Kuoppala
> {
> - /* We're using qword write, offset should be aligned to 8 bytes. */
> - GEM_BUG_ON(
will wait for all cpus to enter
> the stop_machine callback, and those cpus may be waiting for the
> critical section already held.
>
> Fixes: d7085b0faac8 ("drm/i915/gem: Poison stolen pages before use")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by:
s from the HWSP and dispatch it at different
> points around a wrap to see if the value is lost.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 378 +++-
> 1 file changed, 376 insertions(+), 2 d
meline_cacheline *cl;
> +
> + /* Before the request is executed, the timeline/cachline is fixed */
s/cachline/cacheline
Reviewed-by: Mika Kuoppala
> +
> + cl = rcu_dereference_protected(rq->hwsp_cacheline, 1);
> + if (cl)
> + return cl->ggt
a couple of orders of magnitude.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_mmap_gtt.c | 23 ---
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_g
7;s not busy-spin waiting for the
> old heartbeat, but terminate it and start afresh.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deleti
e. The value of 128KiB was found
> by empirical measurement (and verified now with a selftest) on gen9.
>
> Signed-off-by: Chris Wilson
> Cc: sta...@vger.kernel.org
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/Kconfig.debug | 1 +
> drivers/gpu/drm
ting a delay on the GPU
> between requests.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Bruce Chang
> Cc: Joonas Lahtinen
> Cc: sta...@vger.kernel.org
Acked-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> 1 file changed, 3 inse
that it had a tag after reading, tho double does no harm.
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 37 +++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 12 ++--
> 2 files changed, 34 insertions(+), 15 deletions(-)
>
&g
Chris Wilson writes:
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_exec_balancer.c | 46 +++---
> 1 file changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/g
Chris Wilson writes:
> In practice, it turns out that compute likes to use userptr for
> everything, and so in turn so must we.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_exec_schedule.c | 41 +++---
>
Chris Wilson writes:
Needs a commit message like:
Add support for dummyload to be userptr.
Reviewed-by: Mika Kuoppala
> Signed-off-by: Chris Wilson
> ---
> lib/igt_dummyload.c | 87 -
> lib/igt_dummyload.h | 13 --
&
Chris Wilson writes:
> When allocating objects from stolen, memset() the backing store to
> POISON_INUSE (0x5a) to help identify any uninitialised use of a stolen
> object.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gem/i
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-10-07 10:40:59)
>> Chris Wilson writes:
>>
>> > The initial breadcrumb marks the transition from context wait and setup
>> > into the request payload. We use the marker to determine if the request
>> >
Chris Wilson writes:
> The initial breadcrumb marks the transition from context wait and setup
> into the request payload. We use the marker to determine if the request
> is merely waiting to begin, or is inside the payload and hung.
> Forgetting to include a breadcrumb before the user payload wo
; in the ring that includes an expected wa_tail. (That is if the
> ring->tail is already set to rq->wa_tail, including another 8 bytes in
> the check does not invalidate the incremental wrap detection.)
>
> Fixes: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewi
ck.
>
> This impacts tgl/rcs0 as we rely on the heartbeat for our healthcheck for
> the normal preemption detection mechanism is disabled by default.
>
> Testcase: igt/gem_exec_schedule/preempt-hang/rcs0 #tgl
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
Reviewed-by: Mik
ab.freedesktop.org/drm/intel/-/issues/2508
> Testcase: igt/core_hotunplug
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu
Chris Wilson writes:
> Simply check that we support parsing of batches as large as the uAPI
> allows.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> Try a few intermediate object sizes since CI machines do not have enough
> m
only for it flip back
> to a large unsigned value after passing a boundary check.
>
> Fixes: ed13033f0287 ("drm/i915/cmdparser: Only cache the dst vmap")
> Testcase: igt/gen9_exec_parse/bb-large
> Reported-by: "Candelaria, Jared"
> Signed-off-by: Chris Wilson
Chris Wilson writes:
> If we find the GPU didn't update the CSB within 50us, we currently fail
> and eventually reset the GPU. Lets report the value from the mmio space
> as a last resort, it may just stave off an unnecessary GPU reset.
>
> Suggested-by: Mika Kuoppala
I am
that was not covered by our
> previous w/a.
>
> References: d8f505311717 ("drm/i915/icl: Forcibly evict stale csb entries")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Bruce Chang
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.
ict stale csb entries")
References: HSDES#22011327657, HSDES#1508287568
> Suggested-by: Bruce Chang
> Signed-off-by: Chris Wilson
> Cc: Bruce Chang
> Cc: Mika Kuoppala
> Cc: sta...@vger.kernel.org # v5.4
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 21
1.929369] ret_from_fork+0x22/0x30
> <4> [211.929382] Modules linked in: vgem snd_hda_codec_hdmi
> snd_hda_codec_generic ledtrig_audio i915 coretemp crct10dif_pclmul
> crc32_pclmul ghash_clmulni_intel snd_hda_intel snd_intel_dspcfg snd_hda_codec
> snd_hwdep snd_hda_core e1000
Tvrtko Ursulin writes:
> From: Tvrtko Ursulin
>
> As GEM contexts are closed we want to have the DRM client remember how
> much GPU time they used (per class) so later we can used it for smarter
> purposes.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Mika Kuoppala
engines;
> } stale;
> +
> + /**
> + * @past_runtime: Accumulation of freed intel_context pphwsp runtimes.
We are tracking runtime in per engine hw context, which pphwsp is just
part of (first page of it).
If this is also in par with the documentation, good enough.
Revie
es: 6b05030496f7 ("drm/i915: Convert i915_gem_object/client_blt.c to use
> ww locking as well, v2.")
> Signed-off-by: Dan Carpenter
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
&g
From: Thomas Hellström
The hwsp_gtt object is used for sub-allocation and could therefore
be shared by many contexts causing unnecessary contention during
concurrent context pinning.
However since we're currently locking it only for pinning, it remains
resident until we unpin it, and therefore it
ntexts -- but we did not prevent those
> contexts from being resubmitted if they survived the final hangcheck.
>
> Fixes: 9a40bddd47ca ("drm/i915/gt: Expose heartbeat interval via sysfs")
> Testcase: igt/gem_ctx_persistence/heartbeat-stop
> Signed-off-by: Chris Wilson
> Cc
stale csb entries")
References: HSDES#1508287568
> Suggested-by: Bruce Chang
> Signed-off-by: Chris Wilson
> Cc: Bruce Chang
> Cc: Mika Kuoppala
> Cc: sta...@vger.kernel.org # v5.4
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 21 ++---
> 1 fil
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