Re: [Intel-gfx] [PATCH v2] kms_atomic : Added subtest for Single Pipe DBUF validation

wrote: On Tue, Oct 25, 2016 at 02:40:00PM +0530, meghanelogal wrote: Existing DDB algorithm divide the DDB wrt data rate, hence the planes with the less height but same width will be allocated less blocks and watermark are based on width which requires more DDB. With this data the flip may fail.

[Intel-gfx] [PATCH v3] kms_atomic : Added subtest for Single Pipe DBUF validation

Existing DDB algorithm divide the DDB wrt data rate, hence the planes with the less height but same width will be allocated less blocks and watermark are based on width which requires more DDB. With this data the flip may fail. In new DDB algorithm, the DDB is divided based on watermark requiremen

[Intel-gfx] [PATCH v2] kms_atomic : Added subtest for Single Pipe DBUF validation

Existing DDB algorithm divide the DDB wrt data rate, hence the planes with the less height but same width will be allocated less blocks and watermark are based on width which requires more DDB. With this data the flip may fail. In new DDB algorithm, the DDB is divided based on watermark requiremen

[Intel-gfx] [PATCH] kms_atomic : Added subtest for Single Pipe DBUF validation

Existing DDB algorithm divide the DDB wrt data rate, hence the planes with the less height but same width will be allocated less blocks and watermark are based on width which requires more DDB. With this data the flip may fail. In new DDB algorithm, the DDB is divided based on watermark requiremen

[Intel-gfx] [PATCH] demos/intel_sprite_on : Sprite Stress Testing

From: meghanelogal Adding the Sprite Stress Test Feature Signed-off-by: meghanelogal --- demos/intel_sprite_on.c | 653 +-- 1 file changed, 347 insertions(+), 306 deletions(-) diff --git a/demos/intel_sprite_on.c b/demos/intel_sprite_on.c index

[Intel-gfx] [PATCH] demos/intel_sprite_on : Adding Pixel Format Support

From: meghanelogal Adding various pixel format support Signed-off-by: meghanelogal --- demos/intel_sprite_on.c | 81 +++ 1 file changed, 75 insertions(+), 6 deletions(-) diff --git a/demos/intel_sprite_on.c b/demos/intel_sprite_on.c index 23fc56c

[Intel-gfx] [PATCH] tools/intel_reg_write:Adding lib calls for CHT/VLV

From: meghanelogal Calling the library functions for reg read and write Signed-off-by: meghanelogal --- tools/intel_reg_write.c | 28 +--- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/tools/intel_reg_write.c b/tools/intel_reg_write.c index ff4e561

[Intel-gfx] [PATCH] tools/intel_reg_read:Adding lib calls for CHT/VLV

From: meghanelogal Calling the library functions for reg read and write Signed-off-by: meghanelogal --- tools/intel_reg_read.c | 17 +++-- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/tools/intel_reg_read.c b/tools/intel_reg_read.c index c550b02..bdff92c 100644

[Intel-gfx] [PATCH] tools/intel_reg_read: Adding the reg offset for VLV and CHT

From: meghanelogal For VLV and CHT for each register access we need to add base offset of 0x18. Signed-off-by: meghanelogal --- tools/intel_reg_read.c | 20 ++-- 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/tools/intel_reg_read.c b/tools