On Thu, 2020-09-10 at 16:10 +0300, Jani Nikula wrote:
> On Sat, 05 Sep 2020, Xiaolin Zhang wrote:
> > to enable vgpu pv feature, pv capability is introduced for guest by
> > new pv_caps member in struct i915_virtual_gpu and for host GVT by
> > new pv_caps register in struct vgt_if.
> >
> > both o
On Thu, 2020-09-10 at 16:20 +0300, Jani Nikula wrote:
> On Sat, 05 Sep 2020, Xiaolin Zhang wrote:
> > based on the common shared memory, vgpu pv command transport buffer
> > (CTB)
> > protocol is implemented which is a simple pv command buffer ring
> > with pv
> > command descriptor used to perfor
On Thu, 2020-09-10 at 16:16 +0300, Jani Nikula wrote:
> On Sat, 05 Sep 2020, Xiaolin Zhang wrote:
> > To support vgpu pv features, a common shared memory is setup used
> > for
> > communication and data exchange between guest and host GVTg to
> > reduce
> > data access overhead and trap cost.
> >
On Thu, 2020-09-10 at 16:10 +0300, Jani Nikula wrote:
> On Sat, 05 Sep 2020, Xiaolin Zhang wrote:
> > to enable vgpu pv feature, pv capability is introduced for guest by
> > new pv_caps member in struct i915_virtual_gpu and for host GVT by
> > new pv_caps register in struct vgt_if.
> >
> > both o
On 08/23/2019 03:58 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-08-23 07:57:31)
>> vgpu ppgtt notification was split into 2 steps, the first step is to
>> update PVINFO's pdp register and then write PVINFO's g2v_notify register
>> with action code to tirgger ppgtt notification to GVT side
On 07/23/2019 06:37 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-07-23 12:31:57)
>> To enable vgpu pv features, we need to setup a shared memory page
>> which will be used for data exchange directly accessed between both
>> guest and backend i915 driver to avoid emulation trap cost.
>>
>>
On 07/23/2019 05:30 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-07-23 12:31:56)
>> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c
>> b/drivers/gpu/drm/i915/i915_vgpu.c
>> index dbd1fa3..9b37dd1 100644
>> --- a/drivers/gpu/drm/i915/i915_vgpu.c
>> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
>> @
On 07/08/2019 06:41 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-07-08 02:35:18)
>> +static void pv_submit(struct intel_engine_cs *engine,
>> + struct i915_request **out,
>> + struct i915_request **end)
>> +{
>> + struct intel_engine_execlists * const execli
On 07/09/2019 05:12 PM, Chris Wilson wrote:
> Preempt-to-busy uses a GPU semaphore to enforce an idle-barrier across
> preemption, but mediated gvt does not fully support semaphores.
>
> v2: Fiddle around with the flags and settle on using has-semaphores for
> the core bits so that we retain the ab
On 06/24/2019 05:48 PM, Chris Wilson wrote:
> Preempt-to-busy uses a GPU semaphore to enforce an idle-barrier across
> preemption, but mediated gvt does not fully support semaphores.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
> drivers/gpu/drm/i91
On 06/10/2019 03:44 PM, Chris Wilson wrote:
> Quoting Zhang, Xiaolin (2019-06-10 02:32:18)
>> On 06/04/2019 05:01 PM, Chris Wilson wrote:
>>> Quoting Xiaolin Zhang (2019-06-03 07:02:44)
>>>> +static void gen8_ppgtt_clear_4lvl_pv
On 06/04/2019 05:01 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-06-03 07:02:44)
>> +static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
>> + u64 start, u64 length)
>> +{
>> + struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>> +
On 04/29/2019 06:03 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-04-29 04:10:54)
>> +static void pv_submit(struct intel_engine_cs *engine)
>> +{
>> + struct intel_engine_execlists * const execlists = &engine->execlists;
>> + struct execlist_port *port = execlists->port;
>> +
On 03/30/2019 12:05 AM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-03-29 13:32:36)
>> To improve vgpu performance, it could implement some PV optimization
>> such as to reduce the mmio access trap numbers or eliminate certain piece
>> of HW emulation within guest driver to reduce vm exit/vm
On 03/30/2019 03:14 AM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-03-29 13:32:40)
>> + spin_lock(&engine->i915->vgpu.shared_page_lock);
>> + shared_page->ring_id = engine->id;
>> + for (n = 0; n < execlists_num_ports(execlists); n++)
>> + shared_page->descs[n
On 03/29/2019 11:40 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-03-29 13:32:40)
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c
>> b/drivers/gpu/drm/i915/i915_irq.c
>> index 2f78829..28e8ee0 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -3
Ping review, thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; He
Ping review. Thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He
Ping review. Thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He
Ping review, thanks very much.
BRs, Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He
Ping review. Thanks very much.
BRs
Xiaolin
-Original Message-
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-...@lists.freedesktop.org; Zhang, Xiaolin
; Zhenyu Wang ; Wang, Zhi A
; Chris Wilson ; Joonas
Lahtinen ; He; He
Would like to ask ping for review patch set v2. thanks very much.
BRs, Xiaolin
On 10/19/2018 03:27 PM, Zhang, Xiaolin wrote:
> To improve GVTg performance, it could reduce the mmio access trap
> numbers within guest driver in some certain scenarios since mmio
> access trap will intr
On 10/11/2018 04:07 PM, Zhao, Yakui wrote:
>
> On 2018年10月11日 14:14, Xiaolin Zhang wrote:
>> This patch handles ppgtt update from g2v notification.
>>
>> It read out ppgtt pte entries from guest pte tables page and
>> convert them to host pfns.
>>
>> It creates local ppgtt tables and insert the con
On 10/11/2018 05:12 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2018-10-11 07:14:05)
>> It is performance optimization to reduce mmio trap numbers from 4 to
>> 1 durning ELSP porting writing (context submission).
>>
>> When context subission, to cache elsp_data[4] values in
>> the shared page,
On 10/11/2018 04:04 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2018-10-11 07:24:19)
>> To enable pvmmio feature, we need to prepare one 4K shared page
>> which will be accessed by both guest and backend i915 driver.
>>
>> guest i915 allocate one page memory and then the guest physical address
On 10/09/2018 10:34 AM, Zhenyu Wang wrote:
> On 2018.09.28 14:09:45 +0800, Zhang, Xiaolin wrote:
>> On 09/27/2018 07:03 PM, Joonas Lahtinen wrote:
>>> Quoting Xiaolin Zhang (2018-09-27 19:37:46)
>>>> This int type module parameter is used to control the different
>
On 09/27/2018 03:18 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2018-09-27 17:37:47)
>> To enable pvmmio feature, we need to prepare one 4K shared page
>> which will be accessed by both guest and backend i915 driver.
>>
>> guest i915 allocate one page memory and then the guest physical address
On 09/27/2018 07:03 PM, Joonas Lahtinen wrote:
> Quoting Xiaolin Zhang (2018-09-27 19:37:46)
>> This int type module parameter is used to control the different
>> level pvmmio feature for MMIO emulation in GVT.
>>
>> This parameter is default zero, no pvmmio feature enabled.
>>
>> Its permission ty
On 09/27/2018 07:07 PM, Joonas Lahtinen wrote:
> Quoting Xiaolin Zhang (2018-09-27 19:37:45)
>> To improve GVTg performance, it could reduce the mmio access trap
>> numbers within guest driver in some certain scenarios since mmio
>> access trap will introuduce vm exit/vm enter cost.
>>
>> the solut
On 09/27/2018 03:21 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2018-09-27 17:37:48)
>> It is performance optimization to reduce mmio trap numbers from 4 to
>> 1 durning ELSP porting writing (context submission).
>>
>> When context subission, to cache elsp_data[4] values in
>> the shared page,
On 09/28/2017 10:25 PM, Joonas Lahtinen wrote:
On Thu, 2017-09-28 at 10:09 +0800, Xiaolin Zhang wrote:
if vgpu active, the page table entry should be initialized after
allocation and then the hypersivor can ping pages succesuffly,
otherwise hypervisor will ping pages failed and the host will pri
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