nlocks in kvmgt.
Reported-by: Stephen Rothwell
Signed-off-by: Yu Zhang
---
drivers/gpu/drm/i915/gvt/kvmgt.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 60f1a386dd06..b4348256ae95 100644
--
On 2/11/2015 4:06 PM, Daniel Vetter wrote:
On Tue, Feb 10, 2015 at 12:11:02PM +, Tvrtko Ursulin wrote:
On 02/10/2015 11:05 AM, Yu Zhang wrote:
This patch set includes necessary code changes when i915 driver
runs inside a VM. Though ideally we can run an unmodified i915
driver in VM
On 2/10/2015 8:11 PM, Tvrtko Ursulin wrote:
On 02/10/2015 11:05 AM, Yu Zhang wrote:
This patch set includes necessary code changes when i915 driver
runs inside a VM. Though ideally we can run an unmodified i915
driver in VM, adding such enlightenments can greatly reduce the
virtualization
- rebase the code into intel_fbc_update()
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Zhiyuan Lv
---
drivers/gpu/drm/i915/intel_fbc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 7341e87.
side. And the allocated fence number is provided
in PV INFO page structure. By now, the value of fence number is fixed,
but in the future we can relax this limitation, to allocate the fence
registers dynamically from host side.
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Eddie
v
- use #define instead of enum for display readiness
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Zhiyuan Lv
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_dma.c | 8
drivers/gpu/drm/i915/i915_vgpu.h | 4
2 files changed, 12 insertions(+)
diff
or vGPU
v4:
take Tvrtko's comments:
- also use mmio hooks for read operations
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Kevin Tian k
---
drivers/gpu/drm/i915/intel_uncore.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/
is to gen6+
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3c64810..177ff97 100644
--- a/drivers/gp
ballooning functions into i915_vgpu.c
- add kerneldoc to ballooning functions
v4:
take Tvrtko's comments:
- more accurate comments and commit message
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Zhi Wang
Signed-off-by: Eddie Dong
---
drivers/gpu/drm/i915
new callback
routine - vgpu_mm_switch() to set the PP_DIR_BASE by mmio writes.
v2:
take Chris' comments:
- move the code into sanitize_enable_ppgtt()
v4:
take Tvrtko's comments:
- fix the parenthesis alignment warning
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
R
ame i915_vgt_if.h to i915_vgpu.h
v4:
take Tvrtko's comments:
- fix a typo in commit message
- add debug message when vgt version mismatches
- rename low_gmadr/high_gmadr to mappable/non-mappable in PV INFO
structure
Signed-off-by: Yu Zhang
Signed-off-by:
r information carried through
PVINFO is about the number of fence registers. As a global resource,
XenGT also partitions them among VMs.
Other changes are trivial as optimizations, to either reduce the
trap overhead or disable power management features which don't
make sense in a virtualized en
On 12/17/2014 7:06 PM, Gerd Hoffmann wrote:
Hi,
It's not possible to allow guests direct access to the fence registers
though. And if every fence register access traps into the hypervisor
anyway the hypervisor can easily map the guest virtual fence to host
physical fence, so there is no n
On 12/12/2014 9:31 PM, Tvrtko Ursulin wrote:
On 11/13/2014 12:02 PM, Yu Zhang wrote:
In the virtualized environment, forcewake operations are not
necessory for the driver, because mmio accesses will be trapped
necessary
Thanks.
and emulated by the host side, and real forcewake
On 12/12/2014 9:27 PM, Tvrtko Ursulin wrote:
On 11/13/2014 12:02 PM, Yu Zhang wrote:
With Intel GVT-g, GPU power management is controlled by
host driver, so there is no need to provide virtualized
GPU PM support. In the future it might be useful to gather
VM input for freq boost, but now
On 12/15/2014 4:16 PM, Daniel Vetter wrote:
On Thu, Nov 13, 2014 at 08:02:46PM +0800, Yu Zhang wrote:
Display switch logic is added to notify the host side that
current vGPU have a valid surface to show. It does so by
writing the display_ready field in PV INFO page, and then
will be handled
On 12/12/2014 9:13 PM, Tvrtko Ursulin wrote:
On 11/13/2014 12:02 PM, Yu Zhang wrote:
Framebuffer compression is disabled when driver detects it's
running in a Intel GVT-g enlightened VM, because FBC is not
emulated and there is no stolen memory for a vGPU.
v2:
take Chris'
On 12/16/2014 11:15 PM, Tvrtko Ursulin wrote:
Hi,
On 12/16/2014 02:39 PM, Gerd Hoffmann wrote:
Out of curiosity, what will be the mechanism to prevent a vGPU
instance
from ignoring the ballooning data? Must be something in the hypervisor
blocking pass-through access to such domains?
Well, a
On 12/16/2014 9:19 PM, Tvrtko Ursulin wrote:
On 12/16/2014 12:51 PM, Yu, Zhang wrote:
Thank you very much for your thorough review, Tvrtko. :)
On 12/12/2014 1:33 AM, Tvrtko Ursulin wrote:
On 11/13/2014 12:02 PM, Yu Zhang wrote:
Introduce a PV INFO structure, to facilitate the Intel GVT-g
On 12/12/2014 9:07 PM, Tvrtko Ursulin wrote:
On 11/13/2014 12:02 PM, Yu Zhang wrote:
With Intel GVT-g, the fence registers are partitioned by multiple
vGPU instances in different VMs. Routine i915_gem_load() is modified
to reset the num_fence_regs, when the driver detects it's running
On 12/12/2014 9:00 PM, Tvrtko Ursulin wrote:
On 11/13/2014 12:02 PM, Yu Zhang wrote:
With Intel GVT-g, the global graphic memory space is partitioned by
multiple vGPU instances in different VMs. The ballooning code is called
in i915_gem_setup_global_gtt(), utilizing the drm mm allocator APIs
Thank you very much for your thorough review, Tvrtko. :)
On 12/12/2014 1:33 AM, Tvrtko Ursulin wrote:
On 11/13/2014 12:02 PM, Yu Zhang wrote:
Introduce a PV INFO structure, to facilitate the Intel GVT-g
technology, which is a GPU virtualization solution with mediated
pass-through. This page
On 11/14/2014 6:16 PM, Daniel Vetter wrote:
On Thu, Nov 13, 2014 at 08:02:43PM +0800, Yu Zhang wrote:
+ if (low_gm_base < ggtt_vm->start
+ || low_gm_end > dev_priv->gtt.mappable_end
+ || high_gm_base < dev_priv->gtt.mappable_end
+
On 11/14/2014 6:17 PM, Daniel Vetter wrote:
On Thu, Nov 13, 2014 at 08:02:41PM +0800, Yu Zhang wrote:
Intel GVT-g (previously known as XenGT), is a complete GPU
virtualization solution with mediated pass-through for 4th
generation Intel Core processors - Haswell platform. This
technology
With Intel GVT-g, the fence registers are partitioned by multiple
vGPU instances in different VMs. Routine i915_gem_load() is modified
to reset the num_fence_regs, when the driver detects it's running in
a VM. And the allocated fence number is provided in PV INFO page
structure.
Signed-off-b
ocbook
other changes:
- rename i915_vgt_if.h to i915_vgpu.h
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Eddie Dong
---
Documentation/DocBook/drm.tmpl | 5 +++
drivers/gpu/drm/i915/Makefile | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 11 +
drivers/gpu/
ce registers. As a global resource
XenGT also partitions them among VMs.
Other changes are trivial as optimizations, to either reduce the
trap overhead or disable power management features which don't
make sense in a virtualized environment.
Yu Zhang (8):
drm/i915: Introduce a PV INFO page s
new callback
routine - vgpu_mm_switch() to set the PP_DIR_BASE by mmio writes.
v2:
take Chris' comments:
- move the code into sanitize_enable_ppgtt()
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 16
1 file change
Framebuffer compression is disabled when driver detects it's
running in a Intel GVT-g enlightened VM, because FBC is not
emulated and there is no stolen memory for a vGPU.
v2:
take Chris' comments:
- move the code into intel_update_fbc()
Signed-off-by: Yu Zhang
Signed-off-by:
tions into i915_vgpu.c
- add kerneldoc to ballooning functions
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Zhi Wang
Signed-off-by: Eddie Dong
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +++-
drivers/gpu/drm/i915/i915_vgpu.
n
the middle of VM modesetting, e.g. compositing the framebuffer
in the host side.
v2:
- move the notification code outside the 'else' in load sequence
- remove the notification code in intel_crtc_set_config()
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off
is to gen6+
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3bc5d93..3722bd4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/d
PU
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Kevin Tian
---
drivers/gpu/drm/i915/intel_uncore.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index cae27bb..b76c21d 100644
---
In XenGT, GPU power management is controlled by host i915
driver, so there is no need to provide virtualized GPU PM
support. In the future it might be useful to gather VM
input for freq boost, but now let's disable it simply.
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
---
drivers/gp
On 10/23/2014 8:28 PM, Daniel Vetter wrote:
On Thu, Oct 23, 2014 at 03:28:24PM +0800, Yu Zhang wrote:
Empty commit messages aren't good. Even for really simple refactoring
please explain in 1-2 sentences the motivation for the patch, since the
change itself doesn't really say that
Signed-off-by: Yu Zhang
---
drivers/gpu/drm/i915/intel_uncore.c | 76 ++---
1 file changed, 28 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 0b0f4f8..9b228e3 100644
--- a/drivers/gpu
On 10/22/2014 11:33 PM, Daniel Vetter wrote:
On Wed, Oct 22, 2014 at 08:27:50PM +0800, Yu, Zhang wrote:
On 10/22/2014 12:40 AM, Daniel Vetter wrote:
On Thu, Oct 16, 2014 at 02:24:27PM +0800, Yu Zhang wrote:
In the virtualized environment, forcewake operations are not
necessory for the
On 10/22/2014 12:40 AM, Daniel Vetter wrote:
On Thu, Oct 16, 2014 at 02:24:27PM +0800, Yu Zhang wrote:
In the virtualized environment, forcewake operations are not
necessory for the driver, because mmio accesses will be trapped
and emulated by the host side, and real forcewake operations are
On 10/22/2014 12:51 AM, Daniel Vetter wrote:
On Tue, Oct 21, 2014 at 06:16:26PM +0200, Daniel Vetter wrote:
On Fri, Oct 17, 2014 at 01:37:11PM +0800, Yu Zhang wrote:
Intel GVT-g (previously known as XenGT), is a complete GPU
virtualization solution with mediated pass-through for 4th
Hi Daniel,
Thanks a lot for your reply. Indeed, I sent two v2 patches, because
the format of the first v2 patchset is incorrect - I forgot to add the
what changed part in those messages. :)
Yu
On 10/22/2014 12:16 AM, Daniel Vetter wrote:
On Fri, Oct 17, 2014 at 01:37:11PM +0800, Yu Zhang
will reduce many traps and
increase the overall performance for drivers runing in the VM
with Intel GVT-g enhancement.
v2:
take Chris' comments:
- register the mmio hooks in intel_uncore_init()
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Kevin Tian
---
driver
is to gen6+
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 50cf96b..3a80557 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drive
callback
routine - vgpu_mm_switch() to set the PP_DIR_BASE by mmio writes.
v2:
take Chris' comments:
- move the code into sanitize_enable_ppgtt()
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 16
1 file change
Framebuffer compression is disabled when driver detects it's
running in XenGT VM, because XenGT does not provide emulations
for FBC related operations, and we do not expose stolen memory
to the VM.
v2:
take Chris' comments:
- move the code into intel_update_fbc()
Signed-off-by
n the middle of VM modesetting,
e.g. compositing the framebuffer in the host side.
v2:
- move the notification code outside the 'else' in load sequence
- remove the notification code in intel_crtc_set_config()
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Chris and Daniel's comments:
- no guard page between different VMs
- use drm_mm_reserve_node() to do the reservation for ballooning,
instead of the previous drm_mm_insert_node_in_range_generic()
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Zhi
In XenGT, the fence registers are partitioned by multiple vgpu instances
in different VMs. Routine i915_gem_load() is modified to reset the
num_fence_regs, when the driver detects it's runing in a VM. And the
allocated fence numbers is provided in PV INFO page structure.
Signed-off-by: Yu
ce registers. As a global resource
XenGT also partitions them among VMs.
Other changes are trivial as optimizations, to either reduce the
trap overhead or disable power management features which don't
make sense in a virtualized environment.
Yu Zhang (8):
drm/i915: Introduce a PV INFO page structure
i915_check_vgpu()
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Eddie Dong
---
drivers/gpu/drm/i915/i915_drv.h | 12 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 26
drivers/gpu/drm/i915/i915_vgt_if.h | 85 +
drivers/gpu/drm/i915
In XenGT, GPU power management is controlled by host i915
driver, so there is no need to provide virtualized GPU PM
support. In the future it might be useful to gather VM
input for freq boost, but now let's disable it simply.
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
---
drivers/gp
-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Zhi Wang
Signed-off-by: Eddie Dong
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 144 +++-
1 file changed, 141 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm
n the middle of VM modesetting,
e.g. compositing the framebuffer in the host side.
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Zhiyuan Lv
---
drivers/gpu/drm/i915/i915_dma.c| 11 +++
drivers/gpu/drm/i915/i915_vgt_if.h | 8
2 files changed, 19 inser
Framebuffer compression is disabled when driver detects it's
running in XenGT VM, because XenGT does not provide emulations
for FBC related operations, and we do not expose stolen memory
to the VM.
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Zhiyuan Lv
---
drivers/gp
page. If true, the pointer,
vgpu.vgt_info is initialized, and intel_vgpu_active() is used by
checking this pointer to conclude if gpu is virtualized with Intel
GVT-g. By now, it will return true only when the driver is running
in the XenGT environment on HSW.
Signed-off-by: Yu Zhang
Signed-off-by:
callback
routine - vgpu_mm_switch() to set the PP_DIR_BASE by mmio writes.
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915
In XenGT, the fence registers are partitioned by multiple vgpu instances
in different VMs. Routine i915_gem_load() is modified to reset the
num_fence_regs, when the driver detects it's runing in a VM. And the
allocated fence numbers is provided in PV INFO page structure.
Signed-off-by: Yu
will reduce many traps and
increase the overall performance for drivers runing in the VM
with Intel GVT-g enhancement.
Signed-off-by: Yu Zhang
Signed-off-by: Jike Song
Signed-off-by: Kevin Tian
---
drivers/gpu/drm/i915/intel_uncore.c | 20
1 file changed, 20 insertions
ce registers. As a global resource
XenGT also partitions them among VMs.
Other changes are trivial as optimizations, to either reduce the
trap overhead or disable power management features which don't
make sense in a virtualized environment.
Yu Zhang (8):
drm/i915: Introduce a PV INFO page structure
On 9/29/2014 8:40 PM, Jike Song wrote:
On 09/29/2014 08:16 PM, Chris Wilson wrote:
On Mon, Sep 29, 2014 at 07:44:56PM +0800, Jike Song wrote:
On 09/19/2014 03:25 PM, Chris Wilson wrote:
Now, given that these are simply trapped memory access, wouldn't it be
simply to have:
struct i915_virtua
On 9/29/2014 7:44 PM, Jike Song wrote:
On 09/19/2014 03:25 PM, Chris Wilson wrote:
Now, given that these are simply trapped memory access, wouldn't it be
simply to have:
struct i915_virtual_gpu {
struct vgt_if *if;
} vgu;
static inline bool intel_vgpu_active(struct drm_i915_private *i915
On 9/26/2014 4:48 PM, Chris Wilson wrote:
On Fri, Sep 26, 2014 at 04:26:20PM +0800, Zhang, Yu wrote:
Hi Chris & Daniel,
Thanks for your comments. Following are my understandings about
the changes needed for this patch:
1> We do not need the guard page anymore between different VMs. For
th
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