[Intel-gfx] image in IOMMU based SVM

2017-03-07 Thread Yang, Rong R
Hi, I am working on IOMMU based SVM, based on Mika's patch. I have a question that does svm context support legacy buffer object? If not, how to support tiled image in svm context. Thanks, Yang Rong ___ Intel-gfx mailing list Intel-gfx@lists.freedeskt

Re: [Intel-gfx] [PATCH] drm/915/glk: Enable pooled EUs for Geminilake

2017-02-27 Thread Yang, Rong R
eira, Ander > Sent: Friday, February 24, 2017 21:13 > To: intel-gfx@lists.freedesktop.org > Cc: Conselvan De Oliveira, Ander ; > Arun Siluvery ; Kuoppala, Mika > ; Ursulin, Tvrtko ; > Yang, Rong R > Subject: [PATCH] drm/915/glk: Enable pooled EUs for Geminilake > > Gemin

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/bxt: Fix inadvertent CPU snooping due to incorrect MOCS config

2016-07-14 Thread Yang, Rong R
> -Original Message- > From: Deak, Imre > Sent: Friday, July 1, 2016 21:40 > To: intel-gfx@lists.freedesktop.org > Cc: Ville Syrjälä ; Chris Wilson wilson.co.uk>; Yang, Rong R ; Zhao, Yakui > ; Tamminen, Eero T > Subject: [PATCH v3 2/3] drm/i915/bxt: Fix inadver

Re: [Intel-gfx] [PATCH] intel: Export pooled EU and min no. of eus in a pool.

2016-07-05 Thread Yang, Rong R
Yes, it is libdrm patch. I have merged the beignet patch right now, but still depend on the libdrm patch, I will resend it to libdrm now. Thanks. > -Original Message- > From: Arun Siluvery [mailto:arun.siluv...@linux.intel.com] > Sent: Tuesday, July 5, 2016 18:01 > To:

Re: [Intel-gfx] [Beignet] [PATCH] intel: Export pooled EU and min no. of eus in a pool.

2016-06-30 Thread Yang, Rong R
Hi, Arun, Beignet patch is reviewed by ruiling, can you have to export them? Thanks, Yang Rong > -Original Message- > From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of > Arun Siluvery > Sent: Wednesday, June 15, 2016 16:17 > To: Yang

Re: [Intel-gfx] [PATCH v6 2/2] drm/i915: Add soft-pinning API for execbuffer

2015-11-04 Thread Yang, Rong R
> -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Chris Wilson > Sent: Wednesday, September 9, 2015 22:25 > To: Winiarski, Michal > Cc: intel-gfx@lists.freedesktop.org; Kristian Høgsberg; dri- > de...@lists.freedesktop.org; Goel, Akash;

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Add soft-pinning API for execbuffer

2015-10-22 Thread Yang, Rong R
> -Original Message- > From: Daniel, Thomas > Sent: Wednesday, October 21, 2015 23:11 > To: Daniel Vetter > Cc: Chris Wilson; intel-gfx@lists.freedesktop.org; Belgaumkar, Vinay; Yang, > Rong R > Subject: RE: [Intel-gfx] [PATCH 3/3] drm/i915: Add soft-pinning

Re: [Intel-gfx] [Mesa-dev] [rong.r.y...@intel.com: How user space applications load registers on HSW?]

2014-05-12 Thread Yang, Rong R
al Message- From: Kenneth Graunke [mailto:kenn...@whitecape.org] Sent: Wednesday, May 07, 2014 2:57 AM To: Yang, Rong R Cc: Ben Widawsky; mesa-dev; intel-gfx Subject: Re: [Mesa-dev] [rong.r.y...@intel.com: [Intel-gfx] How user space applications load registers on HSW?] On 05/06/2014 08:26:1

[Intel-gfx] How user space applications load registers on HSW?

2014-05-06 Thread Yang, Rong R
Hi, I am developing the HSW's OCL driver in the linux. I encounter a LRI problem on HSW. Some gpgpu's applications, which use the shared local memory, must load the L3CTRLREG2 and L3CTRLREG3 registers to allocate the SLM in the L3 cache. So I add L3CTRLREG2 and L3CTRLREG3 to the gen7_render_reg