On 9/20/2018 1:36 AM, Anusha Srivatsa wrote:
From: Animesh Manna
ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.
v2: (James Ausmus)
- Also handle ICL as GEN9_LP in i915_drm_suspend_late and
i915_drm_suspend_early
- Add DC9 to gen9_dc_m
On 10/3/2018 10:36 AM, Vivi, Rodrigo wrote:
On Oct 2, 2018, at 9:20 PM, Yadav, Jyoti R wrote:
DC5 and DC6 counter register tells about residency of DC5 and DC6.
These registers are same for SKL and ICL.
v2 : Remove csr_version check.
Added generic check regarding DC counters for
Deak, Imre ;
Pandiyan, Dhinakaran ; Atwood, Matthew S
; Yadav, Jyoti R ; Bowman,
Casey G
Subject: [PATCH] drm/i915/psr: Enable AUX-A IO power well on ICL for PSR
PSR requires AUX IO power well to be enabled. This was already in place for
CNL, extend this for ICL too. Not enabling the power well resu
Yeah, Thanks for the "Acked-by" Rodrigo.
I request Imre/Anusha to review/acknowledge the same.
Regards
Jyoti
-Original Message-
From: Vivi, Rodrigo
Sent: Tuesday, September 4, 2018 11:02 AM
To: Yadav, Jyoti R
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PAT
Hi Imre,
I also checked in Bspec. Good catch:)
FW size = (End address - Start Address) + 1
Will update the patch also. Thanks for quickly reviewing the patch.
Regards
Jyoti
_
On 8/29/2018 2:51 PM, Imre Deak wrote:
On Tue, Aug 28, 2018 at 03:24:19PM -0400, Jyoti Yadav wrote:
From: Jyoti
T
Hi Jani,
I am already debugging this issue. Issue got reproduced when we are
locally running the icl_dmc_ver1_07.bin on ICL HW.
We could not see this issue with previous FW version icl_dmc_ver1_01.bin
file.
Already in discussion with DMC FW folks. There are two FW stepping
integrated in l
From: Jyoti Yadav
BIOS programs few of PWM related registers during initial boot.
But during System suspend those registers are cleared.
This test aims to check whether display programs those registers properly
after
system resume.
Also checks brightness programming during DP
From: Jyoti Yadav
BIOS programs few of PWM related registers during initial boot.
But during System suspend those registers are cleared.
This test aims to check whether display programs those registers properly
after
system resume.
Also checks brightness programming during DP
Hi Anusha,
I think we should also add "HAS_CSR" capability, which is being
exercised inside intel_csr_ucode_init() path.
For ICL, inside intel_device_info structure we should add has_csr = 1,
otherwise below check will fail and function will return from there itself.
if (!HAS_CSR(dev_priv))
From: Jyoti Yadav
Added few subtests to cover below gaps.
1. scaler with pixelformat and tiling.
2. scaler with rotation
3. scaler with multiple planes
4. scaler with multi pipe
5. scaler with clipping/clamping scenario
Signed-off-by: Jyoti Yadav
---
tes
Hi Jani,
Thanks for finding time to review the patch. Please find my comments inline.
Regards
Jyoti
-Original Message-
From: Nikula, Jani
Sent: Monday, January 9, 2017 2:30 PM
To: Yadav, Jyoti R ; intel-gfx@lists.freedesktop.org
Cc: Kahola, Mika ; Syrjala, Ville
; mi-jenkins-ci
From: Jenkins Val
Signed-off-by: Jyoti Yadav
---
tests/Makefile.am | 3 +-
tests/Makefile.sources | 1 +
tests/mipi_sequence_verification.c | 201 +
3 files changed, 204 insertions(+), 1 deletion(-)
create mode 100644 tests/m
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