> On Thu, Jan 16, 2025 at 01:33:43PM +0000, Murthy, Arun R wrote:
> > > On Thu, Jan 16, 2025 at 12:33:20PM +0000, Murthy, Arun R wrote:
> > > > > > > On Fri, Jan 10, 2025 at 01:15:29AM +0530, Arun R Murthy wrote:
> > > > > > > > D
> On Thu, Jan 16, 2025 at 12:33:20PM +0000, Murthy, Arun R wrote:
> > > > > On Fri, Jan 10, 2025 at 01:15:29AM +0530, Arun R Murthy wrote:
> > > > > > Display Histogram is an array of bins and can be generated in
> > > > > > many ways referred
> On Thu, Jan 16, 2025 at 12:33:30PM +0000, Murthy, Arun R wrote:
> > > > > On Fri, Jan 10, 2025 at 01:15:30AM +0530, Arun R Murthy wrote:
> > > > > > ImageEnhancemenT(IET) hardware interpolates the LUT value to
> > > > > > genera
> > > On Fri, Jan 10, 2025 at 01:15:30AM +0530, Arun R Murthy wrote:
> > > > ImageEnhancemenT(IET) hardware interpolates the LUT value to
> > > > generate the enhanced output image. LUT takes an input value,
> > > > outputs a new value based on the data within the LUT. 1D LUT can
> > > > remap indi
> > > On Fri, Jan 10, 2025 at 01:15:29AM +0530, Arun R Murthy wrote:
> > > > Display Histogram is an array of bins and can be generated in many
> > > > ways referred to as modes.
> > > > Ex: HSV max(RGB), Wighted RGB etc.
> > > >
> > > > Understanding the histogram data format(Ex: HSV max(RGB))
> >
> > > > -Original Message-
> > > > From: dri-devel On
> > > > Behalf Of Arun R Murthy
> > > > Sent: Wednesday, January 8, 2025 11:09 AM
> > > > To: dri-de...@lists.freedesktop.org;
> > > > intel-gfx@lists.freedesktop
> > > > 68b31c0563a4c0 100644
> > > > --- a/drivers/gpu/drm/drm_plane.c
> > > > +++ b/drivers/gpu/drm/drm_plane.c
> > > > @@ -191,7 +191,10 @@ modifiers_ptr(struct drm_format_modifier_blob
> > > > *blob)
> > > > return (struct drm_format_modifier *)(((char *)blob) + blob-
> > > > >modifiers
> On Fri, Jan 10, 2025 at 01:15:35AM +0530, Arun R Murthy wrote:
> > Histogram added as part of i915/display driver. Adding the same for xe
> > as well.
> >
> > Signed-off-by: Arun R Murthy
> > Reviewed-by: Suraj Kandpal
>
> Is building of the Xe driver broken between the previous commit and thi
> On Fri, Jan 10, 2025 at 01:15:29AM +0530, Arun R Murthy wrote:
> > Display Histogram is an array of bins and can be generated in many
> > ways referred to as modes.
> > Ex: HSV max(RGB), Wighted RGB etc.
> >
> > Understanding the histogram data format(Ex: HSV max(RGB)) Histogram is
> > just the p
> On Fri, Jan 10, 2025 at 01:15:30AM +0530, Arun R Murthy wrote:
> > ImageEnhancemenT(IET) hardware interpolates the LUT value to generate
> > the enhanced output image. LUT takes an input value, outputs a new
> > value based on the data within the LUT. 1D LUT can remap individual
> > input values
> > -Original Message-
> > From: dri-devel On Behalf Of
> > Arun R Murthy
> > Sent: Wednesday, January 8, 2025 11:09 AM
> > To: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > intel- x...@lists.freedesktop.org
> > Cc: Murth
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Arun R Murthy
> > Sent: Wednesday, January 8, 2025 11:09 AM
> > To: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > intel- x...@lists.freedesktop.org
> > Cc: Murth
> On Tue, Dec 10, 2024 at 05:52:38PM +0000, Murthy, Arun R wrote:
> > > On Tue, Dec 10, 2024 at 08:42:36AM +0000, Murthy, Arun R wrote:
> > > > > On Mon, Dec 09, 2024 at 09:54:55PM +0530, Arun R Murthy wrote:
> > > > > > Add variables
> > -Original Message-
> > From: Intel-xe On Behalf Of
> > Arun R Murthy
> > Sent: Monday, November 11, 2024 2:56 PM
> > To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Murthy, Arun R
> > Subject: [PATCHv4] dr
> > On Mon, Nov 18, 2024 at 01:23:14PM +0530, Arun R Murthy wrote:
> > > Expose drm plane function to create formats/modifiers blob. This
> > > function can be used to expose list of supported formats/modifiers
> > > for sync/async flips.
> > >
> > > Signed-off-by: Arun R Murthy
> > > ---
> > > d
> On Tue, Dec 10, 2024 at 08:42:36AM +0000, Murthy, Arun R wrote:
> > > On Mon, Dec 09, 2024 at 09:54:55PM +0530, Arun R Murthy wrote:
> > > > Add variables for histogram drm_property, its corrsponding
> > > > crtc_state variables and define the structure p
> On Mon, Dec 09, 2024 at 09:54:54PM +0530, Arun R Murthy wrote:
> > Display histogram is a hardware functionality where a statistics for 'x'
> > number of frames is generated to form a histogram data. This is
> > notified to the user via histogram event. Compositor will then upon
> > sensing the h
> On Mon, Dec 09, 2024 at 09:54:55PM +0530, Arun R Murthy wrote:
> > Add variables for histogram drm_property, its corrsponding crtc_state
> > variables and define the structure pointed by the blob property.
> >
> > struct drm_histogram and drm_iet defined in
> > include/uapi/drm/drm_mode.h
> >
> >
> On Thu, Dec 05, 2024 at 04:29:55PM +0000, Murthy, Arun R wrote:
> > > > > -Original Message-
> > > > > From: Dmitry Baryshkov
> > > > > Sent: Wednesday, December 4, 2024 5:17 PM
> > > > > To: Murthy, Arun R
&g
> > > -Original Message-
> > > From: Dmitry Baryshkov
> > > Sent: Wednesday, December 4, 2024 5:17 PM
> > > To: Murthy, Arun R
> > > Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > dri- de...@lists.freed
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Wednesday, December 4, 2024 5:17 PM
> To: Murthy, Arun R
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Subject: Re: [PATCHv2 01/10] drm/crtc: Add
> On Mon, Nov 18, 2024 at 01:23:14PM +0530, Arun R Murthy wrote:
> > Expose drm plane function to create formats/modifiers blob. This
> > function can be used to expose list of supported formats/modifiers for
> > sync/async flips.
> >
> > Signed-off-by: Arun R Murthy
> > ---
> > drivers/gpu/drm/d
> > > > On Thu, Nov 21, 2024 at 05:56:00PM +0530, Arun R Murthy wrote:
> > > > > CRTC properties have been added for enable/disable histogram,
> > > > > reading the histogram data and writing the IET data.
> > > > > "HISTOGRAM_EN" is the crtc property to enable/disable the global
> > > > > histogra
> > > On Thu, Nov 21, 2024 at 05:56:00PM +0530, Arun R Murthy wrote:
> > > > CRTC properties have been added for enable/disable histogram,
> > > > reading the histogram data and writing the IET data.
> > > > "HISTOGRAM_EN" is the crtc property to enable/disable the global
> > > > histogram and take
> > > > +static void write_iet(struct intel_display *display, enum pipe pipe,
> > > > + u32 *data)
> > > > +{
> > > > + int i;
> > > > +
> > > > + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) {
> > > > + if (DISPLAY_VER(display) >= 20)
> > > > +
> On Thu, Nov 21, 2024 at 05:56:00PM +0530, Arun R Murthy wrote:
> > CRTC properties have been added for enable/disable histogram, reading
> > the histogram data and writing the IET data.
> > "HISTOGRAM_EN" is the crtc property to enable/disable the global
> > histogram and takes a value 0/1 accord
Of Arun R
> Murthy
> Sent: Thursday, November 21, 2024 5:56 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCHv5 2/8] drm/i915/histogram: Add support for histogram
>
> Statistic
> > -Original Message-
> > From: dri-devel On Behalf Of
> > Arun R Murthy
> > Sent: Thursday, November 21, 2024 5:56 PM
> > To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > dri- de...@lists.freedesktop.org
> > Cc: Murthy, A
> > -Original Message-
> > From: Intel-xe On Behalf Of
> > Arun R Murthy
> > Sent: Thursday, November 21, 2024 5:56 PM
> > To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > dri- de...@lists.freedesktop.org
> > Cc: Murthy, A
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Arun R Murthy
> > Sent: Tuesday, November 19, 2024 4:15 PM
> > To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > dri- de...@lists.freedesktop.org
> > Cc: Murthy,
> -Original Message-
> From: Kandpal, Suraj
> Sent: Wednesday, November 20, 2024 3:55 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: RE: [PATCHv4 7/
> > -Original Message-
> > From: Intel-xe On Behalf Of
> > Arun R Murthy
> > Sent: Tuesday, November 19, 2024 4:15 PM
> > To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > dri- de...@lists.freedesktop.org
> > Cc: Murthy,
> > CRTC properties have been added for enable/disable histogram, reading
> > the histogram data and writing the IET data.
> > "HISTOGRAM_EN" is the crtc property to enable/disable the global
> > histogram and takes a value 0/1 accordingly.
> > "Histogram" is a crtc property to read the binary hist
> > Statistics is generated from the image frame that is coming to display
> > and an event is sent to user after reading this histogram data.
> > This statistics/histogram is then shared with the user upon getting a
> > request from user. User can then use this histogram and generate an
> > enhanc
> On Tue, 19 Nov 2024, Arun R Murthy wrote:
> > Upon enabling histogram an interrupt is trigerred after the generation
> > of the statistics. This patch registers the histogram interrupt and
> > handles the interrupt.
> >
> > v2: Added intel_crtc backpointer to intel_histogram struct (Jani)
> >
> On Tue, 19 Nov 2024 at 10:55, Arun R Murthy
> wrote:
> > The corresponding mutter changes to enable/disable histogram, read the
> > histogram data, communicate with the library and write the enhanced
> > data back to the KMD is also pushed for review at
> > https://gitlab.gnome.org/GNOME/mutter/
> > Upon enabling histogram an interrupt is trigerred after the generation
> > of the statistics. This patch registers the histogram interrupt and
> > handles the interrupt.
> >
> > v2: Added intel_crtc backpointer to intel_histogram struct (Jani)
> > Removed histogram_wq and instead use dev_pr
> > +
> > + if (DISPLAY_VER(intel_display) < 20)
> > + return;
> > +
> > + /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST
> & 128b/132b */
> > + hblank = DIV_ROUND_UP((DIV_ROUND_UP(adjusted_mode->htotal -
> > +adjusted_mode->hdisplay, 4) * bpp_x16), symbol_size
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, November 6, 2024 7:31 PM
> To: Murthy, Arun R
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Subject: Re: [PATCH 1/4] drm/plane: A
> -Original Message-
> From: Intel-gfx On Behalf Of Clint
> Taylor
> Sent: Friday, October 25, 2024 4:01 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: [PATCH v4 03/11] drm/i915/xe3lpd: Add check to see if edp over type c
> is allowed
>
> From: Suraj
> > Subject: Re: [PATCH] drm/i915/display: plane property for async
> > supported modifiers
> >
> > On Wed, Oct 16, 2024 at 04:54:09PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 16, 2024 at 04:30:19PM +0300, Ville Syrjälä wrote:
> > > > On Wed, Oct 16, 2024 at 11:06:26AM +0530, Arun R Murthy wro
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, September 26, 2024 3:44 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: Re: [PATCH 1/7] drm/i
> -Original Message-
> From: Jani Nikula
> Sent: Tuesday, October 22, 2024 1:04 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: Re: [PATCHv2] drm/i915/dp: Guarantee a minimum HBlank tim
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, October 16, 2024 7:31 PM
> To: Murthy, Arun R
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/display: pla
> >> > +static __inline__ void set_bin_index_0(struct intel_display
> >> > +*display, enum pipe pipe)
> >> ^^
> >>
> >> Why?
> >>
> > Sorry, didn't get your question. Is it why "enum pipe pipe"
>
> No, why __inline__? What's the point?
>
> (I tried to underline it with ^
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, September 25, 2024 2:18 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Srikanth V, NagaVenkata
> ; Kandpal, Suraj
>
> Subject: Re
> > .../gpu/drm/i915/display/intel_histogram.c| 111 +-
> > .../drm/i915/display/intel_histogram_reg.h| 25
> > 2 files changed, 105 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c
> > b/drivers/gpu/drm/i915/display/i
> > > +static int intel_histogram_enable(struct intel_crtc *intel_crtc) {
> > > + struct intel_display *display = to_intel_display(intel_crtc);
> > > + struct intel_histogram *histogram = intel_crtc->histogram;
> > > + int pipe = intel_crtc->pipe;
> > > + u64 res;
> > > + u32 gbandthreshold;
> > >
> > +struct intel_histogram {
> > + struct intel_crtc *crtc;
> > + struct delayed_work histogram_int_work;
>
> I think I mentioned this in my previous comment but naming this just work
> should be fine since I don’t see any other work for histogram So itll be
> called as
> histogram->work whi
> > + /*
> > +* During LT, Tx shall read DPCD 02216h before DPCD 00202h
> to 00207h and
> > +* 0200Ch through 0200Fh.
> > +*/
>
> I really like comments that are actual helpful sentences. Why do I I need to
> look
> up what 02216h and 00202h-00207h ar
> On Thu, 12 Sep 2024, Arun R Murthy wrote:
> > DP Source should be reading AUX_RD interval after we get adjusted
> > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in DP
> > Source)
>
> I don't think that's correct. See below.
>
Will correct the statement.
> > Signed-off-by:
> > > > - /*
> > > > -* The delay may get updated. The transmitter shall
> > > > read the
> > > > -* delay before link status during link training.
> > > > -*/
> > > > - delay_us =
> > > > drm_dp_128b132b_read_aux_rd_inter
> > diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c
> > b/drivers/gpu/drm/i915/display/intel_histogram.c
> > index 189f7ccd6df8..9c31a7d83362 100644
> > --- a/drivers/gpu/drm/i915/display/intel_histogram.c
> > +++ b/drivers/gpu/drm/i915/display/intel_histogram.c
> > @@ -26,38 +26,41 @@
> -Original Message-
> From: Kandpal, Suraj
> Sent: Wednesday, September 11, 2024 4:20 PM
> To: Murthy, Arun R ; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: RE: [PATCHv2 5/5] drm/i915/display/histogram: Histogram changes
> -Original Message-
> From: Kandpal, Suraj
> Sent: Wednesday, September 11, 2024 4:10 PM
> To: Murthy, Arun R ; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: RE: [PATCHv2 4/5] drm/i915/histogram: histogram delay counter
> doesnt reset
>
>
&
> > The delay counter for histogram does not reset and as a result the
> > histogram bin never gets updated. Woraround would be to use save and
> > restore histogram register.
>
> Lets not mention the issue in the commit message just what the patch/ WA is
> doing The issue is very well describe in
> > #define INTEL_CRTC_FUNCS \
> > .set_config = drm_atomic_helper_set_config, \
> > .destroy = intel_crtc_destroy, \
> > @@ -229,7 +326,9 @@ static int intel_crtc_late_register(struct drm_crtc
> *crtc)
> > .set_crc_source = intel_crtc_set_crc_source, \
> > .verify_crc_source = int
> > > > +static int intel_crtc_set_property(struct drm_crtc *crtc,
> > > > + struct drm_crtc_state *state,
> > > > + struct drm_property *property,
> > > > + u64 val)
> > > > +{
> > > > + struct
> > > +static int intel_crtc_get_property(struct drm_crtc *crtc,
> > > +const struct drm_crtc_state *state,
> > > +struct drm_property *property,
> > > +uint64_t *val)
> > > +{
> > > + struct drm_i915_private *i915
> > diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c
> > b/drivers/gpu/drm/i915/display/intel_histogram.c
> > index 45e968e00af6..83ba826a7a89 100644
> > --- a/drivers/gpu/drm/i915/display/intel_histogram.c
> > +++ b/drivers/gpu/drm/i915/display/intel_histogram.c
> > @@ -19,12 +19,83 @@
> > Upon enabling histogram an interrupt is trigerred after the generation
> > of the statistics. This patch registers the histogram interrupt and
> > handles the interrupt.
> >
> > v2: Added intel_crtc backpointer to intel_histogram struct (Jani)
> > Removed histogram_wq and instead use dev_pr
> > > > +#define HISTOGRAM_GUARDBAND_THRESHOLD_DEFAULT 300//
> > 3.0% of
> > > > the pipe's current pixel count.
> > > > +#define HISTOGRAM_GUARDBAND_PRECISION_FACTOR 1 //
> > Precision
> > > > factor for threshold guardband.
> > > > +#define HISTOGRAM_DEFAULT_GUARDBAND_DELAY 0x04
> > > >
> > pipe's current pixel count.
> > +#define HISTOGRAM_GUARDBAND_PRECISION_FACTOR 1 // Precision
> > factor for threshold guardband.
> > +#define HISTOGRAM_DEFAULT_GUARDBAND_DELAY 0x04
> > +
> > +struct intel_histogram {
> > + struct drm_i915_private *i915;
>
> Lets use intel_display here
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, September 12, 2024 2:36 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Srikanth V, NagaVenkata
>
> Subject: Re: [PATCH 1/3] drm/i915/d
> On Thu, 12 Sep 2024, Arun R Murthy wrote:
> > DP Source should be reading AUX_RD interval after we get adjusted
> > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in DP
> > Source)
>
> Please explain why.
As per the DP 2.1 spec section 3.5.2.16.1
"The transmitter shall finish
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, September 12, 2024 2:32 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Srikanth V, NagaVenkata
>
> Subject: Re: [PATCH 1/3] drm/i915/d
> > +static void intel_histogram_handle_int_work(struct work_struct *work) {
> > + struct intel_histogram *histogram = container_of(work,
> > + struct intel_histogram, handle_histogram_int_work.work);
> > + struct drm_i915_private *i915 = histogram->i915;
> > + struct intel_crtc *in
> > @@ -7503,6 +7508,14 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > * FIXME get rid of this funny new->old swapping
> > */
> > old_crtc_state->dsb = fetch_and_zero(&new_crtc_state-
> > >dsb);
> > +
>
> Since there is a wai
> > @@ -7503,6 +7508,14 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > * FIXME get rid of this funny new->old swapping
> > */
> > old_crtc_state->dsb = fetch_and_zero(&new_crtc_state-
> > >dsb);
> > +
>
> Since there is a wai
> > @@ -161,12 +191,19 @@ static int intel_histogram_enable(struct
> > intel_crtc
> > *intel_crtc)
> > * enable DPST_CTL Histogram mode
> > * Clear DPST_CTL Bin Reg function select to TC
> > */
> > - intel_de_rmw(i915, DPST_CTL(pipe),
> > -DPST_CTL_BIN_REG_FUNC_SEL
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Arun R Murthy
> > Sent: Wednesday, August 21, 2024 3:54 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Murthy, Arun R
> > Subject: [PATCHv2 1/5] drm/i915/display: Add support for
> > > The sharpness property requires the use of one of the scaler so need
> > > to set the sharpness scaler coefficient values.
> > > These values are based on experiments and vary for different tap
> > > value/win size. These values are normalized by taking the sum of all
> > > values and then di
> > > +static int
> > > +intel_atomic_replace_property_blob_from_id(struct drm_device *dev,
> > > +struct drm_property_blob **blob,
> > > +u64 blob_id,
> > > +ssize_t expected_size,
> > > +
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 29, 2024 8:18 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nikula, Jani ; Vivi, Rodrigo
> ;
> De Marchi, Lucas ; Sousa, Gustavo
>
> Subject: [PATCH v2 5/6] drm/i91
> -Original Message-
> From: Intel-gfx On Behalf Of Nemesa
> Garg
> Sent: Monday, July 8, 2024 1:39 PM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Garg, Nemesa
> Subject: [4/5] drm/i915/display: Add registers and compute the strength
>
> Add new registers
> -Original Message-
> From: Intel-gfx On Behalf Of Nemesa
> Garg
> Sent: Monday, July 8, 2024 1:39 PM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Garg, Nemesa
> Subject: [3/5] drm/i915/display: Enable the second scaler for sharpness
>
> As only second sc
> -Original Message-
> From: Intel-gfx On Behalf Of Nemesa
> Garg
> Sent: Monday, July 8, 2024 1:39 PM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Garg, Nemesa
> Subject: [v4 2/5] drm/i915/display: Compute the scaler filter coefficients
>
> The sharpness
> -Original Message-
> From: Intel-gfx On Behalf Of Nemesa
> Garg
> Sent: Monday, July 8, 2024 1:39 PM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Garg, Nemesa
> Subject: [1/5] drm: Introduce sharpness mode property
>
> Introduces the new crtc property "S
> -Original Message-
> From: Jani Nikula
> Sent: Tuesday, August 27, 2024 1:41 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/i915/display: BMG supports UHBR13.5
>
> On Tue, 27 Aug 2024, Ja
> -Original Message-
> From: Jani Nikula
> Sent: Tuesday, August 27, 2024 1:11 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: Re: [PATCH] drm/i915/display: BMG supports UHBR13.5
>
>
> -Original Message-
> From: Kulkarni, Vandita
> Sent: Thursday, August 22, 2024 4:24 PM
> To: Murthy, Arun R ; intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 1/5] drm/i915/display: Add support for histogram
>
> > -Original Message-
> >
> -Original Message-
> From: Kulkarni, Vandita
> Sent: Monday, August 5, 2024 12:16 PM
> To: Murthy, Arun R ; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: RE: [PATCH 1/5] drm/i915/display: Add support for histogram
>
> > -Original Messa
> > +static int intel_histogram_enable(struct intel_crtc *intel_crtc) {
> > + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev);
> > + struct intel_histogram *histogram = intel_crtc->histogram;
> > + int pipe = intel_crtc->pipe;
> > + u64 res;
> > + u32 gbandthreshold;
> > +
>
> -Original Message-
> From: Deak, Imre
> Sent: Tuesday, August 6, 2024 10:11 PM
> To: Murthy, Arun R
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/xe/pm: Change HPD to polling on runtime suspend
>
> On Tue, Au
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Wednesday, July 31, 2024 2:51 PM
> To: Murthy, Arun R
> Cc: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] RFC: drm/drm_plane: Expose the plane capability and
> interop
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Wednesday, July 31, 2024 2:04 PM
> To: Murthy, Arun R
> Cc: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] RFC: drm/drm_plane: Expose the plane capability and
> interoperab
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Tuesday, July 30, 2024 4:21 AM
> To: Murthy, Arun R
> Cc: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] RFC: drm/drm_plane: Expose the plane capability and
> interoperabi
> -Original Message-
> From: Deak, Imre
> Sent: Monday, July 29, 2024 8:15 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kandpal, Suraj ; Murthy, Arun R
>
> Subject: [PATCH v2 09/14] drm/i915/dp_mst: Reduce the link parameters in BW
> order after LT failures
>
Gentle Reminder!
Any comments?
Thanks and Regards,
Arun R Murthy
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, July 9, 2024 1:17 PM
> To: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R
> Su
> -Original Message-
> From: Deak, Imre
> Sent: Thursday, July 25, 2024 5:15 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 06/14] drm/i915/dp: Send only a single modeset-retry
> uevent for a commit
>
> On Thu, Jul 2
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, July 24, 2024 4:50 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 07/14] drm/i915/dp: Add a separate function to reduce the
> link parameters
>
> On Wed, Jul 2
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, July 24, 2024 4:46 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 06/14] drm/i915/dp: Send only a single modeset-retry
> uevent for a commit
>
> On Wed, Jul 2
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 07/14] drm/i915/dp: Add a separate function to reduce the link
> parameters
>
> A follow-up patch will add an alternative way to r
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 06/14] drm/i915/dp: Send only a single modeset-retry uevent
> for a commit
>
> There are multiple failure cases a modeset-retry
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Thursday, July 4, 2024 1:57 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Deak, Imre
> ; Nikula, Jani
> Subject: [PATCH v2 1/1] drm/i915/display: Cache adpative sync caps to use it
> later
>
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Monday, June 10, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K
> Subject: [PATCH v16 2/9] drm/i915: Separate VRR related register definitions
>
> Move VRR related register definition
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Thursday, May 9, 2024 1:29 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nikula, Jani
>
> Subject: [PATCH v8 4/7] Add refresh rate divider to struct representing AS SDP
>
> Add target_rr_divider
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Thursday, May 9, 2024 1:28 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nikula, Jani
>
> Subject: [PATCH v8 3/7] drm/i915: Compute CMRR and calculate vtotal
>
> Compute Fixed Average Vtotal/CMRR
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Thursday, May 9, 2024 1:28 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nikula, Jani
>
> Subject: [PATCH v8 2/7] drm/i915: Add Enable/Disable for CMRR based on VRR
> state
>
> Add CMRR/Fixed Avera
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Thursday, May 9, 2024 1:28 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nikula, Jani
>
> Subject: [PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR
> registers
>
> Add register definit
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