On 06/12 11:11, Ville Syrjälä wrote:
> On Thu, Jun 12, 2014 at 03:37:18PM +0800, Lee, Chon Ming wrote:
> > On 06/12 08:14, S, Deepak wrote:
> > >
> > >
> > > On 6/11/2014 10:26 PM, Ville Syrjälä wrote:
> > > >On Fri, Jun 06, 2014 at 08:03:20AM
On 06/12 08:14, S, Deepak wrote:
>
>
> On 6/11/2014 10:26 PM, Ville Syrjälä wrote:
> >On Fri, Jun 06, 2014 at 08:03:20AM -0700, Jesse Barnes wrote:
> >>On Fri, 6 Jun 2014 11:29:24 +0300
> >>Ville Syrjälä wrote:
> >>
> >>>On Thu, Jun 05, 2014 at 01:49:34PM -0700, Jesse Barnes wrote:
> This ma
On 05/19 14:48, Matt Roper wrote:
> Intel hardware allows the primary plane to be disabled independently of
> the CRTC. Provide custom primary plane handling to allow this.
>
> v8:
> - Pin/unpin properly when clipping causes the primary plane to be
>disabled when it has previously been enabl
On 04/25 20:14, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The ascii art version of the DPIO diagram gets mangled by docbook, so
> we can't use it there. Insted provide another version built using
> .
>
> Signed-off-by: Ville Syrjälä
When generating drm.tmpl to html, it say
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Wednesday, May 21, 2014 4:50 PM
> To: Lee, Chon Ming
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Add a brief description of
>
On 04/25 20:14, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Document the internal structure of the VLV display PHY a bit to help
> people understand how the different register blocks relate to each
> other.
>
> v2: Add a bit more text
> Make it a DOC: comment, but leave th
On 05/15 12:21, Matt Roper wrote:
> Intel hardware allows the primary plane to be disabled independently of
> the CRTC. Provide custom primary plane handling to allow this.
>
> v7:
> - Clip primary plane to invisible when crtc is disabled since
>intel_crtc->config.pipe_src_{w,h} may be garba
> -Original Message-
> From: Rob Clark [mailto:robdcl...@gmail.com]
> Sent: Friday, May 16, 2014 11:05 AM
> To: Lee, Chon Ming
> Cc: Roper, Matthew D; Intel Graphics Development; dri-
> de...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/4]
On 04/30 10:07, Matt Roper wrote:
> Pull the parameter checking from drm_primary_helper_update() out into
> its own function; drivers that provide their own setplane()
> implementations rather than using the helper may still want to share
> this parameter checking logic.
>
> A few of the checks he
On 12/20 12:32, Paulo Zanoni wrote:
> 2013/12/19 Daniel Vetter :
> > On Thu, Dec 19, 2013 at 10:12 PM, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> When I forked haswell_crtc_enable I copied all the code from
> >> ironlake_crtc_enable. The last piece of the function contains a big
> >> c
Cc back the the mailing list.
On 11/07 22:35, Lee, Chon Ming wrote:
> On 11/07 16:21, Ville Syrjälä wrote:
> > On Thu, Nov 07, 2013 at 03:23:27PM +0800, Chon Ming Lee wrote:
> > > The max frequency reporting is not correct. But there is already an
> > > existing
&g
On 11/07 14:46, Ville Syrjälä wrote:
> On Thu, Nov 07, 2013 at 03:23:26PM +0800, Chon Ming Lee wrote:
> > For DDR data rate reporting by Punit in PUNIT_GPU_FREQ_STS, the actual
> > data encoding is 00b=800, 01b=1066, 10b=1333, 11b=1333.
> >
> > Some premium VLV sku will get the DDR_DATA_RATE set a
On 11/06 14:02, Ville Syrjälä wrote:
> > -#define _DPIO_IREF_CTL_A 0x8040
> > -#define _DPIO_IREF_CTL_B 0x8060
> > -#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)
> > +#define _VLV_PLL_DW10_CH0 0x8040
> > +#define _VLV_PLL_DW10_CH1
e
> intel_drv.h cleanup.
> - Shut up warnings in i915_debugfs.c
>
> v3: Use the right CONFIG variable, spotted by Chon Ming.
>
> Cc: Lee, Chon Ming
> Cc: David Herrmann
> Signed-off-by: Daniel Vetter
> ---
Look good to me this series.
Reviewed-by: Chon Ming
On 10/08 17:44, Daniel Vetter wrote:
>
> mutex_lock(&dev->mode_config.fb_lock);
> list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index f221631..057ddeb 100644
> --- a/drivers/gpu/drm/i9
On 09/26 14:58, Jesse Barnes wrote:
> On Thu, 26 Sep 2013 23:51:52 +0200
> Daniel Vetter wrote:
>
> > On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote:
> > > This fixes resume on my test platform, since I think some DPIO bits need
> > > recalibration.
> > >
> > > References: https://
On 09/24 18:18, Ville Syrjälä wrote:
> On Tue, Sep 24, 2013 at 03:14:27PM +0800, Chon Ming Lee wrote:
> > Without the DPIO cmnreset, the PLL fail to lock. This should have
> > done by BIOS.
> >
> > v2: Move this to intel_uncore_sanitize to allow it to get call during
> > resume path. (Daniel)
> >
On 09/24 15:54, Ville Syrjälä wrote:
> On Tue, Sep 24, 2013 at 05:47:57PM +0800, Chon Ming Lee wrote:
> > CDCLK is used to generate the gmbus clock. This is normally done by
> > BIOS. Program the value if the BIOS-less system doesn't do it.
> >
> > v2: Move this to intel_i2c_reset to allow reprog
On 09/12 18:30, Daniel Vetter wrote:
> On Fri, Sep 13, 2013 at 5:59 AM, Chon Ming Lee
> wrote:
> > In non PC system, such as IVI, may not use BIOS, instead it uses boot
> > loader with only minimal system initialization. Most of the time, boot
> > loader doesn't come with VBIOS, and depends on d
On 09/05 11:35, Jani Nikula wrote:
> On Thu, 05 Sep 2013, Chon Ming Lee wrote:
> > The additional pipe parameter will use to select which phy to target
> > for.
> >
> > Signed-off-by: Chon Ming Lee
> > ---
>
> [snip]
>
> > diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> > b/drivers/gpu/dr
DERRMR is documented in vlv bspec.
Regards,
Chon Ming
On Sep 4, 2013, at 5:42 PM, "Daniel Vetter" wrote:
> On Wed, Sep 4, 2013 at 11:28 AM, Lee, Chon Ming
> wrote:
>> This patch causes VLV hang, look like ring buffer lockup.
>>
>> This is the message.
>
This patch causes VLV hang, look like ring buffer lockup.
This is the message.
[drm] stuck on render ring
I haven't look at the bspec for the different between VLV and Ivybridge on this
yet. Just see anyone have any clue why this might fail in VLV.
On 08/29 21:07, Daniel Vetter wrote:
> On Mon,
On 08/30 11:00, Jani Nikula wrote:
>
> [Okay, I missed Daniel's review, and noticed I hadn't actually hit send
> on this one either... but here goes anyway...]
>
> On Fri, 30 Aug 2013, Chon Ming Lee wrote:
> > For DP pll settings, there is only two golden configs. Instead of running
> > through
On 08/30 10:28, Jani Nikula wrote:
> On Fri, 30 Aug 2013, Chon Ming Lee wrote:
> > eDP 1.4 supports 4-5 extra link rates in additional to current 2 link
> > rate. Create a structure to store the DPLL divisor data to improve
> > readability.
>
> DP 1.2 already supports 3 link rates, right?
Yes,
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