[Intel-gfx] [PATCH v6 0/3] Support 64 bpp half float formats

h: https://gitlab.freedesktop.org/strassek/kmscube/commits/fp16 Kevin Strasser (3): drm/fourcc: Add 64 bpp half float formats drm/i915: Refactor icl_is_hdr_plane drm/i915/icl: Implement half float formats drivers/gpu/drm/drm_fourcc.c | 4 ++ drivers/gpu/drm/i915/intel_atomic.c | 3 +- drive

[Intel-gfx] [PATCH v6 2/3] drm/i915: Refactor icl_is_hdr_plane

David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Kevin Strasser Reviewed-by: Ville Syrjälä Reviewed-by: Maarten Lankhorst Reviewed-by: Adam Jackson --- drivers/gpu/drm/i915/intel_atomic.c | 3 ++- drivers/gpu/drm/i915/intel_display.c | 7 +-- drivers/gpu/drm

[Intel-gfx] [PATCH v6 3/3] drm/i915/icl: Implement half float formats

etter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Kevin Strasser Reviewed-by: Ville Syrjälä Reviewed-by: Maarten Lankhorst Reviewed-by: Adam Jackson --- drivers/gpu/drm/i915/intel_display.c | 22 +++ drivers/gpu/drm/i915/intel_sprite.c | 72 ++-- 2

[Intel-gfx] [PATCH v6 1/3] drm/fourcc: Add 64 bpp half float formats

Signed-off-by: Kevin Strasser Reviewed-by: Ville Syrjälä Reviewed-by: Maarten Lankhorst Reviewed-by: Adam Jackson --- drivers/gpu/drm/drm_fourcc.c | 4 include/uapi/drm/drm_fourcc.h | 11 +++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers

[Intel-gfx] [PATCH v5 3/3] drm/i915/icl: Implement half float formats

x27;t use icl_is_hdr_plane too early v3: - Use refactored icl_is_hdr_plane (Ville) - Use u32 instead of uint32_t (Ville) Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Kevin Strasser Reviewed-by:

[Intel-gfx] [PATCH v5 2/3] drm/i915: Refactor icl_is_hdr_plane

aniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Kevin Strasser Reviewed-by: Ville Syrjälä Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_atomic.c | 3 ++- drivers/gpu/drm/i915/intel_display.c | 7 +-- drivers/gpu/drm/i915/intel_drv.h | 7 --- drivers/gp

[Intel-gfx] [PATCH v5 1/3] drm/fourcc: Add 64 bpp half float formats

...@lists.freedesktop.org Signed-off-by: Kevin Strasser Reviewed-by: Ville Syrjälä Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/drm_fourcc.c | 4 include/uapi/drm/drm_fourcc.h | 11 +++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm

[Intel-gfx] [PATCH v5 0/3] Support 64 bpp half float formats

mmits/fp16 Kevin Strasser (3): drm/fourcc: Add 64 bpp half float formats drm/i915: Refactor icl_is_hdr_plane drm/i915/icl: Implement half float formats drivers/gpu/drm/drm_fourcc.c | 4 ++ drivers/gpu/drm/i915/intel_atomic.c | 3 +- drivers/gpu/drm/i915/intel_disp

[Intel-gfx] [PATCH v4 2/3] drm/i915: Refactor icl_is_hdr_plane

aniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Kevin Strasser Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_atomic.c | 3 ++- drivers/gpu/drm/i915/intel_display.c | 5 +++-- drivers/gpu/drm/i915/intel_drv.h | 7 --- drivers/gpu/drm/i915/intel_sprite.c | 6 +++-

[Intel-gfx] [PATCH v4 0/3] Support 64 bpp half float formats

mmits/fp16 Kevin Strasser (3): drm/fourcc: Add 64 bpp half float formats drm/i915: Refactor icl_is_hdr_plane drm/i915/icl: Implement half float formats drivers/gpu/drm/drm_fourcc.c | 4 ++ drivers/gpu/drm/i915/intel_atomic.c | 3 +- drivers/gpu/drm/i915/intel_disp

[Intel-gfx] [PATCH v4 1/3] drm/fourcc: Add 64 bpp half float formats

://patchwork.kernel.org/patch/10072545/ v2: - Fixed cpp (Ville) - Added detail pixel formatting (Ville) - Ordered formats in header (Ville) Cc: Tina Zhang Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Kevin Strasser

[Intel-gfx] [PATCH v4 3/3] drm/i915/icl: Implement half float formats

x27;t use icl_is_hdr_plane too early v3: - Use refactored icl_is_hdr_plane (Ville) - Use u32 instead of uint32_t (Ville) Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Kevin Strasser Reviewed-by:

[Intel-gfx] [PATCH v3 3/3] drm/i915/icl: Implement half float formats

x27;t use icl_is_hdr_plane too early v3: - Use refactored icl_is_hdr_plane (Ville) - Use u32 instead of uint32_t (Ville) Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Kevin Strasser --- drivers/gp

[Intel-gfx] [PATCH v3 2/3] drm/i915: Refactor icl_is_hdr_plane

ff-by: Kevin Strasser --- drivers/gpu/drm/i915/intel_atomic.c | 4 +++- drivers/gpu/drm/i915/intel_display.c | 5 +++-- drivers/gpu/drm/i915/intel_drv.h | 7 --- drivers/gpu/drm/i915/intel_sprite.c | 6 +++--- 4 files changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH v3 1/3] drm/fourcc: Add 64 bpp half float formats

://patchwork.kernel.org/patch/10072545/ v2: - Fixed cpp (Ville) - Added detail pixel formatting (Ville) - Ordered formats in header (Ville) Cc: Tina Zhang Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Kevin Strasser

[Intel-gfx] [PATCH v3 0/3] Support 64 bpp half float formats

mmits/fp16 Kevin Strasser (3): drm/fourcc: Add 64 bpp half float formats drm/i915: Refactor icl_is_hdr_plane drm/i915/icl: Implement half float formats drivers/gpu/drm/drm_fourcc.c | 4 ++ drivers/gpu/drm/i915/intel_atomic.c | 4 +- drivers/gpu/drm/i915/intel_disp

[Intel-gfx] [PATCH v2 RESEND 1/2] drm/fourcc: Add 64 bpp half float formats

://patchwork.kernel.org/patch/10072545/ v2: - Fixed cpp (Ville) - Added detail pixel formatting (Ville) - Ordered formats in header (Ville) Signed-off-by: Kevin Strasser Cc: Tina Zhang Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org

[Intel-gfx] [PATCH v2 RESEND 2/2] drm/i915/icl: Implement half float formats

x27;t use icl_is_hdr_plane too early Signed-off-by: Kevin Strasser Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org --- drivers/gpu/drm/i915/intel_display.c | 22 drivers/gpu/drm/i915/intel_sprite.c

[Intel-gfx] [PATCH v2 RESEND 0/2] Support 64 bpp half float formats

mmits/fp16 Kevin Strasser (2): drm/fourcc: Add 64 bpp half float formats drm/i915/icl: Implement half float formats drivers/gpu/drm/drm_fourcc.c | 4 +++ drivers/gpu/drm/i915/intel_display.c | 22 drivers/gpu/drm/i915/intel_spri

[Intel-gfx] [PATCH v2 2/2] drm/i915/icl: Implement half float formats

x27;t use icl_is_hdr_plane too early Signed-off-by: Kevin Strasser Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org --- drivers/gpu/drm/i915/intel_display.c | 22 drivers/gpu/drm/i915/intel_sprite.c

[Intel-gfx] [PATCH v2 1/2] drm/fourcc: Add 64 bpp half float formats

://patchwork.kernel.org/patch/10072545/ v2: - Fixed cpp (Ville) - Added detail pixel formatting (Ville) - Ordered formats in header (Ville) Signed-off-by: Kevin Strasser Cc: Tina Zhang Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org

[Intel-gfx] [PATCH v2 0/2] Support 64 bpp half float formats

added to modetest: https://gitlab.freedesktop.org/strassek/drm/commits/fp16 To serve as a smoke test of the whole stack I have a modified version of kmscube: https://gitlab.freedesktop.org/strassek/kmscube/commits/fp16 Kevin Strasser (2): drm/fourcc: Add 64 bpp half float formats drm/i91

[Intel-gfx] [PATCH 1/3] drm/fourcc: Add 64 bpp half float formats

that might contain uint pixel data. This patch attempts to address the feedback provided when 2 of these formats were previosly proposed: https://patchwork.kernel.org/patch/10072545/ Signed-off-by: Kevin Strasser Cc: Tina Zhang Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David

[Intel-gfx] [PATCH 2/3] drm: Add optional PIXEL_NORMALIZE_RANGE property to drm_plane

Add an optional property to allow applications to indicate what range their floating point pixel data is normalized to. Drivers are free to choose what ranges they want to support and can attach this property to each plane that actually supports floating point formats Signed-off-by: Kevin

[Intel-gfx] [PATCH 0/3] Support 64 bpp half float formats

This series defines new formats and adds a plane property to be used for floating point framebuffer content. Implementation is then added to i915. I have shared an IGT branch which adds test coverage for the new formats: https://github.com/strassek/xorg-intel-gpu-tools/tree/fp16 Kevin Strasser

[Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

is currently undefined. As such, the pixel normalize register is enabled iff the framebuffer contains floating point pixel data. Signed-off-by: Kevin Strasser Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org

Re: [Intel-gfx] [PATCH v2] drm/i915/hsw: keep gamma and CSC enabled for primary plane disable

gt; > > > > > > > On Thu, Oct 15, 2015 at 12:51 AM, Kevin Strasser > > > > wrote: > > > > > On HSW the crc differs between black and disabled primary planes, > > > > > causing an > > > > > assert to fail in the kms_unive

Re: [Intel-gfx] [PATCH] drm/i915: respect previous reg values on primary plane disable

On Thu, Oct 15, 2015 at 11:20:59AM +0300, Ville Syrjälä wrote: > On Wed, Oct 14, 2015 at 01:33:57PM -0700, Kevin Strasser wrote: > > On Wed, Oct 14, 2015 at 10:48:52PM +0300, Ville Syrjälä wrote: > > > Does it? I just tried it on IVB, and behaves just like you said. So not >

[Intel-gfx] [PATCH v2] drm/i915/hsw: keep gamma and CSC enabled for primary plane disable

gamma and CSC bits enabled for plane disable path on HSW. v2: Avoid use of RMW Keep path unchanged for non-HSW users Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89331 Testcase: igt/kms_universal_plane/universal-plane-pipe-A-functional Signed-off-by: Kevin Strasser --- drivers/gpu

Re: [Intel-gfx] [PATCH] drm/i915: respect previous reg values on primary plane disable

On Wed, Oct 14, 2015 at 10:48:52PM +0300, Ville Syrjälä wrote: > On Wed, Oct 14, 2015 at 11:59:59AM -0700, Kevin Strasser wrote: [...] > > Just to level set, these cases will produce different CRCs on HSW: > > 1. Primary plane disabled, gamma correction disabled > > 2. P

Re: [Intel-gfx] [PATCH] drm/i915: respect previous reg values on primary plane disable

On Wed, Oct 14, 2015 at 03:22:23PM +0300, Ville Syrjälä wrote: > On Wed, Oct 14, 2015 at 01:12:27PM +0100, Chris Wilson wrote: > > On Wed, Oct 14, 2015 at 03:07:41PM +0300, Ville Syrjälä wrote: > > > On Tue, Oct 13, 2015 at 02:24:41PM -0700, Ke

Re: [Intel-gfx] [PATCH] drm/i915: respect previous reg values on primary plane disable

On Wed, Oct 14, 2015 at 10:58:29AM +0300, Jani Nikula wrote: > On Wed, 14 Oct 2015, Kevin Strasser wrote: > > On HSW the crc differs between black and disabled primary planes, causing an > > assert to fail in the kms_universal_plane test. It seems that things like > > gam

[Intel-gfx] [PATCH] drm/i915: respect previous reg values on primary plane disable

enable bit instead of clearing the control register, making the disable path more similar to that of the sprite plane. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89331 Testcase: igt/kms_universal_plane Signed-off-by: Kevin Strasser --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file