On 1/16/2025 03:52, Krzysztof Karas wrote:
Hi John,
From: John Harrison
To aid debug of sporadic issues, include the requested frequency in
the debug message as well as the actual frequency. That way we know
for certain that the clamping is not because the driver forgot to ask
.
Fixes: 28ff6520a34d ("drm/i915/guc: Update GuC debugfs to support new GuC")
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Matthew Brost
---
I believe this should fix issue #13343, but I wasn't able to repro
the bug to confirm that it is indeed gone with this cha
On 12/24/2024 11:10, Daniele Ceraolo Spurio wrote:
On 12/24/2024 10:13 AM, John Harrison wrote:
On 12/23/2024 15:20, Daniele Ceraolo Spurio wrote:
On 12/20/2024 5:19 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Add debug info to help investigate a very rare bug:
https
On 12/23/2024 15:20, Daniele Ceraolo Spurio wrote:
On 12/20/2024 5:19 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Add debug info to help investigate a very rare bug:
https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13385
Signed-off-by: John Harrison
---
drivers/gpu
hn)
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/dri
On 11/29/2024 04:12, Andi Shyti wrote:
On Thu, Nov 28, 2024 at 06:32:28PM -0800, John Harrison wrote:
On 11/28/2024 13:28, Eugene Kobyak wrote:
When the intel_context structure contains NULL,
it raises a NULL pointer dereference error in drm_info().
Fixes: e8a3319c31a1 ("drm/i915: Allow
s/12309
Cc: John Harrison
Cc: # v6.3+
Signed-off-by: Eugene Kobyak
---
v2:
- return drm_info to separate condition
v3:
- create separate condition which generate string if intel_context exist
v4:
- rollback and add check intel_context in log condition
drivers/gpu/drm/i915/i915_gpu_e
On 11/21/2024 16:31, John Harrison wrote:
On 11/18/2024 15:22, Umesh Nerlige Ramappa wrote:
Active busyness of an engine is calculated using gt timestamp and the
context switch in time. While capturing the gt timestamp, it's possible
that the context switches out. This race could result
, run igt@perf_pmu@busy-hang followed by
igt@perf_pmu@most-busy-idle-check-all for a couple iterations.
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: John Harrison
---
.../gpu
On 11/18/2024 15:22, Umesh Nerlige Ramappa wrote:
On gt reset, if a context is running, then accumulate it's active time
into the busyness counter since there will be no chance for the context
to switch out and update it's run time.
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness sta
m/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 +
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 5 -
2 files changed, 9 insertions(+), 1 de
On 11/20/2024 07:03, Eugene Kobyak wrote:
When the intel_context structure contains NULL,
it raises a NULL pointer dereference error in drm_info().
This patch aims to resolve issue:
https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12309
Signed-off-by: Eugene Kobyak
---
drivers/gpu/drm
On 11/4/2024 15:09, Daniele Ceraolo Spurio wrote:
On 11/4/2024 3:02 PM, John Harrison wrote:
On 10/28/2024 16:31, Daniele Ceraolo Spurio wrote:
All MTL and ARL SKUs share the same GSC FW, but the newer platforms are
only supported in newer blobs. In particular, ARL-S is supported
starting from
and ARL-U are supported from
102.1.15.1926. Therefore, the driver needs to check which specific ARL
subplatform its running on when verifying that the GSC FW is new enough
for it.
Fixes: 2955ae8186c8 ("drm/i915: ARL requires a newer GSC firmware")
Signed-off-by: Daniele Ceraolo Spurio
On 10/12/2024 08:34, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* drm/i915/guc: Enable PXP GuC autoteardown flow (rev4)
*URL:* https://patchwork.freedesktop.org/series/138337/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1383
On 9/26/2024 18:54, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* drm/i915/guc: Enable PXP GuC autoteardown flow (rev3)
*URL:* https://patchwork.freedesktop.org/series/138337/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13833
On 9/18/2024 12:32, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* drm/i915/guc: Enable PXP GuC autoteardown flow (rev2)
*URL:* https://patchwork.freedesktop.org/series/138337/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13833
Please ignore, sent to the wrong mailing list!
John.
On 6/11/2024 14:45, Michal Wajdeczko wrote:
On 11.06.2024 22:32, John Harrison wrote:
On 6/11/2024 07:30, Michal Wajdeczko wrote:
There are many GuC ABI definitions named in the same way by the i915
and Xe drivers, preventing proper generation of the documentation.
Promote GuC ABI definitions
do for the rest of the hardware.
John.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Cc: John Harrison
Michal Wajdeczko (7):
drm/xe/guc: Promote GuC ABI headers to shared location
Documentation/gpu: Separate GuC ABI section
On 5/28/2024 13:21, Matt Roper wrote:
On Fri, May 24, 2024 at 06:41:20PM -0700, john.c.harri...@intel.com wrote:
From: John Harrison
Enable another workaround that is implemented inside the GuC.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 1
CSB FIFO.
To address this issue, the GuC should be killed only after resetting
the requested engines and before calling intel_gt_init_hw().
v2: Improve commit message(John)
Cc: John Harrison
Signed-off-by: Nirmoy Das
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_reset.c | 16
diff simple(John)
Cc: John Harrison
Signed-off-by: Nirmoy Das
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
drivers/gpu/drm/i915/gt
On 4/18/2024 10:10, Nirmoy Das wrote:
Currently intel_gt_reset() happens as follows:
reset_prepare() ---> Sends GDRST to GuC, GuC is in GS_MIA_IN_RESET
do_reset()
intel_gt_reset_all_engines()
*_engine_reset_prepare() -->RESET_CTL expects running GuC
Not technically correct. There is no d
On 4/18/2024 10:10, Nirmoy Das wrote:
intel_engine_reset() not only reset a engine but also
tries to recover it so give it a proper name without
any functional changes.
Not seeing what the difference is. If this was a super low level
function (with an __ prefix for example) then one might expect
On 4/18/2024 10:10, Nirmoy Das wrote:
__intel_gt_reset() is really for resetting engines though
the name might suggest something else. So add two helper functions
to remove confusions with no functional changes.
Technically you only added one and just moved the other :). It already
existed, it j
GuC
*_reset_engines()
intel_gt_init_hw() --> GuC FW loading happens, GuC comes out of
GS_MIA_IN_RESET.
Fix the above flow so that GuC reset happens after all the
engines reset is done.
Cc: John Harrison
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_reset.c | 9 --
dr
://gitlab.freedesktop.org/drm/intel/-/issues/10564
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Reviewed-by: John Harrison
---
.../gpu/drm/i915/selftests/i915_selftest.c| 36 ---
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests
On 3/12/2024 09:24, Matt Roper wrote:
On Thu, Mar 07, 2024 at 06:01:29PM -0800, john.c.harri...@intel.com wrote:
From: John Harrison
An existing workaround has been extended in both platforms affected
and implementation complexity.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt
On 3/7/2024 12:02, Andi Shyti wrote:
Hi Matt,
On Wed, Mar 06, 2024 at 03:46:09PM -0800, Matt Roper wrote:
On Wed, Mar 06, 2024 at 02:22:45AM +0100, Andi Shyti wrote:
The hardware should not dynamically balance the load between CCS
engines. Wa_14019159160 recommends disabling it across all
plat
I dumped them with Windows new line characters.
Here is a new log binary dump.
I moved to the newest TGL GuC firmware from linux-firmware repo.
środa, 21 lutego 2024 12:16 AM, John Harrison john.c.harri...@intel.com
napisał(a):
Hello,
Something is very corrupted with that GuC log. The log consists of
On 2/26/2024 05:25, Nilawar, Badal wrote:
Hi John,
On 04-01-2024 23:35, john.c.harri...@intel.com wrote:
From: John Harrison
Use the new w/a KLV support to enable a MTL w/a. Note, this w/a is a
super-set of Wa_16019325821, so requires turning that one as well as
setting the new flag for
d...@pm.me natur.prod...@pm.me napisał(a):
Hello,
Please see my comments below.
piątek, 9 lutego 2024 2:45 AM, John Harrison john.c.harri...@intel.com
napisał(a):
Hello,
What platform is this on? And which GuC firmware version are you using?
It's TGL. I'm using tgl_guc_70.1.1.bin
On 2/19/2024 12:28, Rodrigo Vivi wrote:
On Fri, Feb 16, 2024 at 10:38:41AM -0800, john.c.harri...@intel.com wrote:
From: John Harrison
The above w/a is required for every platform that the i915 driver
supports. It is fixed on the latest platforms but they are only
supported by Xe instead of
On 2/15/2024 14:34, Andi Shyti wrote:
Hi John,
On Thu, Feb 15, 2024 at 01:23:24PM -0800, John Harrison wrote:
On 2/15/2024 05:59, Andi Shyti wrote:
Since CCS automatic load balancing is disabled, we will impose a
fixed balancing policy that involves setting all the CCS engines
to work
On 2/15/2024 05:59, Andi Shyti wrote:
Since CCS automatic load balancing is disabled, we will impose a
fixed balancing policy that involves setting all the CCS engines
to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the
actual number. As of now, this c
e for LNL and Xe (2024-01-30 09:23:50 -0800)
----
John Harrison (2):
i915: Add GuC v70.19.2 for ADL-P, DG1, DG2, MTL and TGL
xe: First GuC release for LNL and Xe
LICENSE.xe | 39 +++
Hello,
What platform is this on? And which GuC firmware version are you using?
One thing you made need to do is force maximum GT frequency during GuC
load. That is something the i915 driver does. If the system decides the
GPU is idle and drops the frequency to minimum then it can take multiple
On 2/8/2024 00:41, Tvrtko Ursulin wrote:
On 07/02/2024 19:34, John Harrison wrote:
On 2/7/2024 10:49, Tvrtko Ursulin wrote:
On 07/02/2024 18:12, John Harrison wrote:
On 2/7/2024 03:56, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Add a new query to the GuC submission interface version.
Mesa
On 2/7/2024 12:47, Souza, Jose wrote:
On Wed, 2024-02-07 at 11:52 -0800, John Harrison wrote:
On 2/7/2024 11:43, Souza, Jose wrote:
On Wed, 2024-02-07 at 11:34 -0800, John Harrison wrote:
On 2/7/2024 10:49, Tvrtko Ursulin wrote:
On 07/02/2024 18:12, John Harrison wrote:
On 2/7/2024 03:56
On 2/7/2024 11:43, Souza, Jose wrote:
On Wed, 2024-02-07 at 11:34 -0800, John Harrison wrote:
On 2/7/2024 10:49, Tvrtko Ursulin wrote:
On 07/02/2024 18:12, John Harrison wrote:
On 2/7/2024 03:56, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Add a new query to the GuC submission interface
On 2/7/2024 10:49, Tvrtko Ursulin wrote:
On 07/02/2024 18:12, John Harrison wrote:
On 2/7/2024 03:56, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Add a new query to the GuC submission interface version.
Mesa intends to use this information to check for old firmware versions
with a known bug
. Which avoids the need to add any padding
too.
I don't follow how potential 8 vs 32 confusion means jump to 64?!
Compile tested only.
Signed-off-by: Tvrtko Ursulin
Cc: Kenneth Graunke
Cc: Jose Souza
Cc: Sagar Ghuge
Cc: Paulo Zanoni
Cc: John Harrison
Cc: Rodrigo Vivi
Cc: Jani Nikula
On 2/7/2024 03:36, Joonas Lahtinen wrote:
Quoting Tvrtko Ursulin (2024-02-07 10:44:01)
On 06/02/2024 20:51, Souza, Jose wrote:
On Tue, 2024-02-06 at 12:42 -0800, John Harrison wrote:
On 2/6/2024 08:33, Tvrtko Ursulin wrote:
On 01/02/2024 18:25, Souza, Jose wrote:
On Wed, 2024-01-24 at 08:55
h Graunke
Cc: Jose Souza
Cc: Sagar Ghuge
Cc: Paulo Zanoni
Cc: John Harrison
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_getparam.c | 12
include/uapi/drm/i915_drm.h | 13 +
2 files changed, 25 insertions(+)
diff -
On 1/31/2024 10:48, Janusz Krzysztofik wrote:
Hi John,
On Wednesday, 10 January 2024 22:02:16 CET john.c.harri...@intel.com wrote:
From: John Harrison
The context persistence code does things like send super high priority
heartbeat pulses to ensure any leaked context can still be pre-empted
ease that is not ancient.
Signed-off-by: Joonas Lahtinen
Cc: Kenneth Graunke
Cc: Jose Souza
Cc: Sagar Ghuge
Cc: Paulo Zanoni
Cc: John Harrison
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_getparam.c | 12
include/uapi/drm/i
On 1/4/2024 12:34, Daniele Ceraolo Spurio wrote:
On 1/2/2024 2:22 PM, john.c.harri...@intel.com wrote:
From: John Harrison
A failure to load the HuC is occasionally observed where the cause is
believed to be a low GT frequency leading to very long load times.
So a) increase the timeout so
On 12/5/2023 02:39, Nirmoy Das wrote:
Hi John,
On 12/5/2023 10:10 AM, John Harrison wrote:
On 12/5/2023 00:52, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Convert the log
R may have more success, but that is
not something that i915 currently does.
John.
v2: Improve commit message(Tvrtko)
Cc: Tvrtko Ursulin
Cc: John Harrison
Cc: Andi Shyti
Cc: Andrzej Hajda
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5591
Signed-off-by: Nirmoy Das
Review
On 11/21/2023 10:55, Alan Previn wrote:
Add missing tag for "Wa_14019159160 - Case 2" (for existing
PXP code that ensures run alone mode bit is set to allow
PxP-decryption.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletio
On 11/13/2023 07:36, Daniele Ceraolo Spurio wrote:
On 11/9/2023 6:06 PM, John Harrison wrote:
On 11/9/2023 15:54, Daniele Ceraolo Spurio wrote:
On MTL, the HuC is only supported on the media GT, so our validation
check on the module parameter detects an inconsistency on the root GT
(the
m that supports neither HuC nor GuC. There
would be no GuC warning because GuC was not requested. But now there
would also be no HuC warning either.
John.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 5 -
1 file changed, 5 deletions
On 11/9/2023 12:33, Daniele Ceraolo Spurio wrote:
On 11/6/2023 3:59 PM, john.c.harri...@intel.com wrote:
From: John Harrison
There is a mechanism for reporting errors from fire and forget H2G
messages. This is the only way to find out about almost any error in
the GuC backend submission path
On 10/6/2023 17:38, Belgaumkar, Vinay wrote:
On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote:
From: John Harrison
To prevent running out of bits, new w/a enable flags are being added
via a KLV system instead of a 32 bit flags word.
Signed-off-by: John Harrison
---
.../gpu/drm/i915
On 10/6/2023 17:10, Belgaumkar, Vinay wrote:
On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.
Signed-off-by: John
value to the
user as is.
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_engine.h | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 12
drivers/gpu/drm/i915/gt
0-13 11:34:26
-0700)
----
John Harrison (1):
i915: Add GuC v70.13.1 for DG2, TGL, ADL-P and MTL
WHENCE | 8
i915/adlp_guc_70.bin | Bin 297984 -> 342848 bytes
i915/dg2_guc_70.bin | Bin 385856 -> 443200 bytes
On 10/16/2023 15:55, Vinay Belgaumkar wrote:
This bit does not cause an explicit L3 flush. We already use
At all? Or only on newer hardware? And as a genuine spec change or as a
bug / workaround?
If the hardware has re-purposed the bit then it is probably worth at
least adding a comment to th
On 10/13/2023 10:52, Jonathan Cavitt wrote:
Implement GuC-based TLB invalidations and use them on MTL.
Some complexity in the implementation was introduced early on
and will be required for range-based TLB invalidations.
RFC: https://patchwork.freedesktop.org/series/124922/
v2:
- Add missing
ed-by: Tvrtko Ursulin
Acked-by: Nirmoy Das
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 30 ++-
drivers/gpu/drm/i915/gt/intel_tlb.c | 16 +-
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 33
drivers/gpu/drm/i915/gt/uc/intel_guc.h
On 10/13/2023 12:12, John Harrison wrote:
On 10/13/2023 07:42, Cavitt, Jonathan wrote:
-Original Message-
From: Harrison, John C
Sent: Thursday, October 12, 2023 6:08 PM
To: Cavitt, Jonathan ;
intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ;
chris.p.wil...@linux.intel.com
w TLB invalidation
request and cancel all pending requests. The TLB entries will be
invalidated either during GuC reload or on system resume.
Signed-off-by: Fei Yang
Signed-off-by: Jonathan Cavitt
CC: John Harrison
Reviewed-by: Andi Shyti
Acked-by: Tvrtko Ursulin
Acked-by: Nirmoy Das
---
dr
Chang
Signed-off-by: Chris Wilson
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Jonathan Cavitt
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Fei Yang
CC: Andi Shyti
Reviewed-by: Andi Shyti
Acked-by: Tvrtko Ursulin
Acked-by: Nirmoy Das
Reviewed-by: John Harrison
---
drivers/gp
ed-by: Tvrtko Ursulin
Acked-by: Nirmoy Das
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 33 ++-
drivers/gpu/drm/i915/gt/intel_tlb.c | 16 +-
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 33 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.h
athan Cavitt
CC: John Harrison
Reviewed-by: Andi Shyti
Acked-by: Tvrtko Ursulin
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22 ---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 ++
3
On 10/12/2023 06:45, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* drm/i915: Define and use GuC and CTB TLB invalidation
routines (rev2)
*URL:* https://patchwork.freedesktop.org/series/125002/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/P
On 10/12/2023 03:21, Tvrtko Ursulin wrote:
On 21/09/2023 19:20, john.c.harri...@intel.com wrote:
From: John Harrison
If an active context has been banned (e.g. Ctrl+C killed) then it is
likely to be reset as part of evicting it from the hardware. That
results in a 'ignoring context
On 10/11/2023 13:52, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tl
iewed-by: John Harrison
viewed-by: John Harrison
Suggested-by: John Harrison
Signed-off-by: Jonathan Cavitt
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 27 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 2 ++
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu
On 10/11/2023 09:38, Jani Nikula wrote:
Hide gpu error specifics in i915_gpu_error.c. This is also cleaner wrt
conditional compilation, as i915_gpu_error.c is only built with
DRM_I915_CAPTURE_ERROR=y.
With this, we can also make i915_first_error_state() static.
Signed-off-by: Jani Nikula
--
On 10/10/2023 15:30, Cavitt, Jonathan wrote:
-Original Message-
From: Harrison, John C
Sent: Tuesday, October 10, 2023 2:51 PM
To: Cavitt, Jonathan ;
intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ; chris.p.wil...@linux.intel.com; Iddamsetty, Aravind
; Yang, Fei ; Shyti, Andi ;
D
On 10/10/2023 08:02, Jonathan Cavitt wrote:
For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.
Additionally, increase the default timeout from 10 ms to 20 ms
because msleep < 20ms can sle
athan Cavitt
CC: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 21 +--
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 +++
3 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/gp
On 10/10/2023 08:02, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tl
request up to the maximum
number of requests the CT buffer can store.
Suggested-by: John Harrison
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
b/drivers/gpu
On 10/10/2023 09:44, Matt Roper wrote:
On Tue, Oct 10, 2023 at 05:42:28PM +0100, Tvrtko Ursulin wrote:
On 10/10/2023 17:17, Andi Shyti wrote:
Hi Matt,
FIXME: CAT errors are cropping up on MTL. This removes them,
but the real root cause must still be diagnosed.
Do you have a link to specific
On 10/10/2023 07:36, Jonathan Cavitt wrote:
FIXME: CAT errors are cropping up on MTL. This removes them,
but the real root cause must still be diagnosed.
I think 'hides' would be more accurate than 'removes'. At least until we
have a better understanding of the issue.
Also, is there any perfo
On 10/9/2023 19:26, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* More print message helper updates
*URL:* https://patchwork.freedesktop.org/series/124853/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124853v1/index.html
On 10/10/2023 05:15, Andi Shyti wrote:
Hi,
I might have picked up the wrong series and missed some reviews
and the extra patch from Nirmoy with a real use of the
drm_dbg_ratelimited() that John was looking for.
Thanks,
Andi
I just found the original post of this from back in January
(https://p
On 10/9/2023 13:02, Andi Shyti wrote:
Hi John,
...
if (intf_id >= INTEL_GSC_NUM_INTERFACES) {
- drm_warn_once(>->i915->drm, "GSC irq: intf_id %d is out of
range", intf_id);
+ gt_warn_once(gt, "GSC irq: intf_id %d is out of range",
intf_id);
On 10/9/2023 12:54, Andi Shyti wrote:
Hi John,
...
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -71,6 +71,7 @@
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
+#include "gt/intel_gt_print.h"
#include "gt/intel_rc
On 10/9/2023 12:50, Andi Shyti wrote:
Hi John,
...
if (intf_id >= INTEL_GSC_NUM_INTERFACES) {
- drm_warn_once(>->i915->drm, "GSC irq: intf_id %d is out of
range", intf_id);
+ gt_warn_once(gt, "GSC irq: intf_id %d is out of range",
intf_id);
On 10/9/2023 12:43, Andi Shyti wrote:
Hi John,
From: Nirmoy Das
Add a function for ratelimitted debug print.
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Reviewed-by: Matthew Auld
Reviewed-by: Andi Shyti
Signed-off-by: Nirmoy Das
Si
On 10/9/2023 01:56, Tvrtko Ursulin wrote:
On 06/10/2023 19:20, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additio
On 10/9/2023 09:52, Andi Shyti wrote:
Hi,
From: Nirmoy Das
Add a function for ratelimitted debug print.
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Reviewed-by: Matthew Auld
Reviewed-by: Andi Shyti
Signed-off-by: Nirmoy Das
Signed-
On 10/3/2023 13:58, Umesh Nerlige Ramappa wrote:
On Fri, Sep 22, 2023 at 03:25:08PM -0700, john.c.harri...@intel.com
wrote:
From: John Harrison
The GuC has been extended to support a much more friendly engine
busyness interface. So partition the old interface into a 'busy_v1'
spa
Tvrtko, would you have any thoughts on this one?
John.
On 10/4/2023 02:57, Dan Carpenter wrote:
Hello Matthew Brost,
This is a semi-automatic email about new static checker warnings.
The patch 22916bad07a5: "drm/i915: Move submission tasklet to
i915_sched_engine" from Jun 17, 2021, leads to
On 10/5/2023 12:35, Jonathan Cavitt wrote:
For the gt_tlb live selftest, increase the timeout from 10 ms to 200 ms.
200 ms should be more than enough time, and 10 ms was too aggressive.
This is simply waiting for a request to begin executing on an idle
system? How can 10ms possibly be too aggres
On 10/6/2023 03:23, Tvrtko Ursulin wrote:
On 05/10/2023 20:35, Jonathan Cavitt wrote:
...
+static bool intel_gt_is_enabled(const struct intel_gt *gt)
+{
+ /* Check if GT is wedged or suspended */
+ if (intel_gt_is_wedged(gt) || !intel_irqs_enabled(gt->i915))
+ return false;
+
On 10/6/2023 09:18, John Harrison wrote:
On 10/6/2023 03:20, Nirmoy Das wrote:
On 10/6/2023 12:11 PM, Tvrtko Ursulin wrote:
Hi,
Andi asked me to summarize what I think is unaddressed review
feedback so far in order to consolidate and enable hopefully things
to move forward. So I will try
On 10/6/2023 03:20, Nirmoy Das wrote:
On 10/6/2023 12:11 PM, Tvrtko Ursulin wrote:
Hi,
Andi asked me to summarize what I think is unaddressed review
feedback so far in order to consolidate and enable hopefully things
to move forward. So I will try to re-iterate the comments and
questions
On 10/5/2023 12:35, Jonathan Cavitt wrote:
Add device info flags for if GuC TLB Invalidation is enabled.
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff
On 10/5/2023 12:35, Jonathan Cavitt wrote:
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb
On 10/4/2023 13:58, Andi Shyti wrote:
Hi Matt,
The MCR steering semaphore is a shared lock entry between i915
and various firmware components.
Getting the lock might sinchronize on some shared resources.
Sometimes though, it might happen that the firmware forgets to
unlock causing unnecessary
On 10/4/2023 13:09, Andi Shyti wrote:
Hi John,
The MCR steering semaphore is a shared lock entry between i915
and various firmware components.
Getting the lock might sinchronize on some shared resources.
Sometimes though, it might happen that the firmware forgets to
unlock causing unnecessary
On 10/4/2023 12:35, Andi Shyti wrote:
Hi John,
The MCR steering semaphore is a shared lock entry between i915
and various firmware components.
Getting the lock might sinchronize on some shared resources.
Sometimes though, it might happen that the firmware forgets to
unlock causing unnecessary
On 10/4/2023 07:08, Andi Shyti wrote:
Hi Tvrtko,
The MCR steering semaphore is a shared lock entry between i915
and various firmware components.
Getting the lock might sinchronize on some shared resources.
Sometimes though, it might happen that the firmware forgets to
unlock causing unnecessar
On 10/4/2023 12:03, Andi Shyti wrote:
Hi Jonathan,
On Wed, Oct 04, 2023 at 11:36:22AM -0700, Jonathan Cavitt wrote:
Add pci (device info) tags for if GuC TLB Invalidation is enabled.
Since GuC based TLB invalidation is only strictly necessary for MTL
resently, only enable GuC based TLB invalida
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