0 [i915]
> [ 2138.372761] idr_for_each+0xa7/0x160
> [ 2138.372773] ? idr_get_next_ul+0x110/0x110
> [ 2138.372782] ? do_raw_spin_lock+0x10a/0x1d0
> [ 2138.372923] print_context_stats+0x264/0x510 [i915]
>
> Signed-off-by: Chris Wilson
Tested-by: David Weinehall
> ---
>
n (David)
> >
> > Tested-by: David Weinehall
> > Reviewed-by: David Weinehall
> > Cc: Anusha Srivatsa
> > Cc: David Weinehall
> > Signed-off-by: Jani Nikula
>
> So *I* don't need this patch. Please someone tell me this is useful to
> you, and I
On Tue, Apr 24, 2018 at 03:20:16PM +0300, Jani Nikula wrote:
> Use i915.dmc_firmware_path to override default firmware for the platform
> and bypassing version checks.
>
> v2: add missing param struct member declaration (David)
>
> Tested-by: David Weinehall
> Reviewed-by:
m bootup. We already do relegate some configuration to
> asynchronous tasks (such as setting up the fbdev), now do the entire
> probe.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=105622
> Signed-off-by: Chris Wilson
LGTM, and still seems to apply cleanly.
Reviewed
On Thu, Mar 15, 2018 at 05:42:00PM -0700, Rodrigo Vivi wrote:
> On Thu, Mar 15, 2018 at 03:35:02PM +0200, David Weinehall wrote:
> > Since Coffee Lake uses the Kaby Lake DMC it's a safe
> > bet that the debug registers are the same. I haven't
> > double-checked
Since Coffee Lake uses the Kaby Lake DMC it's a safe
bet that the debug registers are the same. I haven't
double-checked that the GLK DMC uses the same registers
as BXT, but it seems as good of a guess as any.
v2: Add parentheses to silence warning
Signed-off-by: David Weinehall
--
Since Coffee Lake uses the Kaby Lake DMC it's a safe
bet that the debug registers are the same. I haven't
double-checked that the GLK DMC uses the same registers
as BXT, but it seems as good of a guess as any.
Signed-off-by: David Weinehall
---
drivers/gpu/drm/i915/i915_debugfs.c |
While the comment singles out Port A or B, the code says Port A or *D*.
Looking at the history it seems that the comment was added after the code,
so it seems likely that the code is correct, not the comment.
CC: Jani Nikula
CC: Rodrigo Vivi
Signed-off-by: David Weinehall
---
drivers/gpu/drm
On Tue, Feb 06, 2018 at 04:36:42PM +0530, Vidya Srinivas wrote:
> From: Chandra Konduru
>
> Display WA #0827:
> Switching the plane format from NV12 to RGB and leaving system idle results
> in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b
> in the CLKGATE_DIS_PSL register for
On Fri, Jan 26, 2018 at 06:49:20PM -0800, Dhinakaran Pandiyan wrote:
> The core already takes care of the delay before retrying. The delay now
> changes to (500, 600)us instead of (500 + 1000, 600 + 1500)us.
Reviewed-by: David Weinehall
> Cc: Rodrigo Vivi
> Signed-off-by: Dhinaka
On Fri, Jan 26, 2018 at 06:49:21PM -0800, Dhinakaran Pandiyan wrote:
> No functional change.
>
> Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/intel_dp.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
>
On Fri, Jan 26, 2018 at 06:49:17PM -0800, Dhinakaran Pandiyan wrote:
> intel_edp_init_dpcd() is cluttered with PSR specific DPCD checks and
> intel_dp.c is huge.
Yes please! Good idea.
> No functional change intended.
Reviewed-by: David Weinehall
> Cc: Rodrigo Vivi
>
On Fri, Jan 26, 2018 at 04:48:05PM +0200, Jani Nikula wrote:
> Currently pch_id gets assigned also when there's no pch. It doesn't look
> like it makes a difference, but do the right thing anyway.
Makes sense.
Reviewed-by: David Weinehall
> Signed-off-by: Jani Nikula
>
On Fri, Jan 26, 2018 at 04:48:04PM +0200, Jani Nikula wrote:
> Save some horizontal space.
Yes, please!
Reviewed-by: David Weinehall
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.c | 189
>
> 1 file changed, 96
On Thu, Jan 25, 2018 at 02:03:29PM -0800, Rodrigo Vivi wrote:
> Now let's finish the Port-F support by adding the
> proper port F detection, irq and power well support.
lgtm,
Reviewed-by: David Weinehall
> v2: Rebase
> v3: Use BIT_ULL
> v4: Cover missed case on ddi init.
ared lanes with port A.
>
Looks good to me, except the dual sets of review comments and
signed-offs by, which seems kind of odd--did you squash two
patches into one?
Anyway, the code looks clean & documented, and the registers
seem to match documentation, so:
Reviewed-by: David Weinehall
&
On Thu, Jan 18, 2018 at 05:06:13PM +0200, Jani Nikula wrote:
> No more sing-a-ling.
LOL, well spotted.
> Reported-by: Adam Jackson
> Signed-off-by: Jani Nikula
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/intel_vbt_defs.h | 6 +++---
> 1 file changed,
On Thu, Jan 18, 2018 at 05:04:59PM +0200, Jani Nikula wrote:
> Update VBT defs to reflect revision 216. While at it, default the
> expected child device struct size to sizeof the size rather than a
> hardcoded value.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i9
On Wed, Dec 20, 2017 at 10:08:53AM +0530, Sharma, Shashank wrote:
> Thanks for the review, David.
>
> My comments, inline.
>
>
> Regards
>
> Shashank
>
>
> On 12/19/2017 3:43 PM, David Weinehall wrote:
> > On Mon, Dec 18, 2017 at 08:15:30PM +0100, Maa
On Mon, Dec 18, 2017 at 08:15:30PM +0100, Maarten Lankhorst wrote:
> Op 14-11-17 om 16:17 schreef Shashank Sharma:
> > Different LSPCON vendors specify their custom methods to pass
> > AVI infoframes to the LSPCON chip, so does Parade tech.
> >
> > This patch adds functions to arrange and write AVI
On Tue, Nov 21, 2017 at 11:54:16PM +0200, Jani Nikula wrote:
> On Tue, 21 Nov 2017, David Weinehall wrote:
> > On Tue, Nov 21, 2017 at 01:51:29PM +0200, Jani Nikula wrote:
> >> Use i915.dmc_firmware_path to override default firmware for the platform
> >> a
:D
But if you chuck in:
param(char *, dmc_firmware_path, NULL) \
in i915_params.h
Things work correctly and you can use:
Tested-by: David Weinehall
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/i915_params.c | 3 +++
> drivers/gpu/drm/i915/intel_csr.c | 9
On Thu, Nov 16, 2017 at 08:24:02PM +0200, David Weinehall wrote:
> On Wed, Nov 08, 2017 at 04:25:42PM +0200, David Weinehall wrote:
> > On Tue, Nov 07, 2017 at 05:18:21PM +0100, Daniel Vetter wrote:
> > > Now that we have CI, and that pm_rpm fully passes (I guess the audi
GEN6_RC_VIDEO_FREQ is deprecated for >= gen10;
don't try to program it.
v2: Use IS_GEN9() instead of INTEL_GEN() and remove comment (Rodrigo)
Signed-off-by: David Weinehall
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 7 ---
1 file changed, 4 insertions(+), 3 d
On Wed, Nov 08, 2017 at 04:25:42PM +0200, David Weinehall wrote:
> On Tue, Nov 07, 2017 at 05:18:21PM +0100, Daniel Vetter wrote:
> > Now that we have CI, and that pm_rpm fully passes (I guess the audio
> > folks have implemented proper runtime pm for snd-hda, hooray, pls
> >
On Mon, Nov 13, 2017 at 10:47:44AM -0800, Rodrigo Vivi wrote:
> On Sat, Nov 11, 2017 at 09:43:44AM +, Sharma, Shashank wrote:
> > Regards
> >
> > Shashank
> >
> >
> > On 11/11/2017 3:56 AM, Rodrigo Vivi wrote:
> > > Starting on GLK we support HDMI 2.0. So this patch only
> > > extend the wor
On Wed, Nov 15, 2017 at 06:06:53PM +, Chris Wilson wrote:
> Quoting David Weinehall (2017-11-15 18:01:41)
> > On Tue, Nov 14, 2017 at 01:51:16PM +, Chris Wilson wrote:
> > > WaEnablePooledEuFor2x6 only applies to preproduction models, unsupported
> > > since com
Wilson
> Cc: Jani Nikula
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 10 --
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 78bf7374
pass:1200 dwarn:3 dfail:1 fail:12
> > skip:1368 time:7765s
> >
> > == Logs ==
> >
> > For more details see:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7115/shards.html
>
> After a few months waiting for David Weinehall to wean himself off his
>
: Valtteri Rantala
With comments below, and unless Altug has objections:
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engi
On Fri, Nov 10, 2017 at 11:53:58AM -0800, Rodrigo Vivi wrote:
> On Fri, Nov 10, 2017 at 02:29:29PM +0000, David Weinehall wrote:
> > GEN6_RC_VIDEO_FREQ is deprecated for >= gen10;
> > don't try to program it.
> >
> > Signed-off-by: David Weinehall
> >
GEN6_RC_VIDEO_FREQ is deprecated for >= gen10;
don't try to program it.
Signed-off-by: David Weinehall
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm
essage, a few years passed since v1 ...
>
> Cc: Takashi Iwai
> Cc: Liam Girdwood
> Cc: "Yang, Libin"
> Cc: "Lin, Mengdong"
> Cc: "Li, Jocelyn"
> Cc: "Kaskinen, Tanu"
> Cc: "Zanoni, Paulo R"
> Signed-off-by: Dani
> struct (Tvrtko, Joonas)
From my point of view (measuring suspend/resume times) knowing
how much time is spent loading GuC & HuC is really useful,
so it's definitely useful information.
Kind regards, David Weinehall
___
Intel-gfx mailing li
ion to attend to Ville's and Chris' review comments
> (this is useful anyway, because the same comments apply whether you go with
> functions or with a static table). I am working on a version that implements
> your suggestions and I will send it as soon as it's ready.
Typically when submitting a changeset that isn't ready to be merged,
you'd tag it RFC or similar.
Kind regards, David Weinehall
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Oct 27, 2017 at 03:05:58PM -0700, Oscar Mateo wrote:
>
>
> On 10/25/2017 05:15 PM, Rodrigo Vivi wrote:
> > CNL adds an extra register for slice/subslice information.
> > Although no SKU is planed with an extra slice let's already
> > handle this extra piece of information so we don't have
On Fri, Oct 27, 2017 at 01:57:09PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 26/10/17 03:32, Chris Wilson wrote:
> > It has been many years since the last confirmed sighting (and fix) of an
> > RC6 related bug (usually a system hang). Remove the parameter to stop
> > users from setting danger
Cc: Nathan Ciobanu
> Cc: Wayne Boyer
> Cc: Joe Konno
> Cc: David Weinehall
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: James Ausmus
I've verified that RC6 works with your patch applied.
Minor comments below, but nothing major. Great work!
Reviewed-by: David Weinehall
; translation table")
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> Cc: David Weinehall
> Cc: Jani Nikula
> Cc: # v4.12+
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/driver
gt; expected to work by HW engineers anyways.
>
> Cc: David Weinehall
> Cc: Mika Kuoppala
> Signed-off-by: Rodrigo Vivi
Sorry, I totally missed out on this one earlier. Looks correct,
and I've tested the patch on our CNL-Y without noticing any
regressions.
Reviewed-by: David W
On Thu, Sep 28, 2017 at 08:19:29PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Add has_psr-flag to gen9lp
> URL : https://patchwork.freedesktop.org/series/28488/
> State : success
>
> == Summary ==
>
> Series 28488v1 drm/i915: Add has_psr-flag to gen9lp
> https://patch
On Thu, Sep 28, 2017 at 08:38:58PM +0100, Chris Wilson wrote:
> I recently tried to update the gen9 feature matrix and to my unpleasant
> surprise found that Kabylake still acted like Broadwell and didn't
> enable the feature. This is because kbl/cfl are inheriting their
> defaults from Broadwell a
On Thu, Sep 28, 2017 at 04:20:29AM +, Rodrigo Vivi wrote:
> On Wed, Sep 27, 2017 at 5:14 AM David Weinehall <
> david.weineh...@linux.intel.com> wrote:
>
> > On Tue, Aug 08, 2017 at 12:50:51PM -0700, Rodrigo Vivi wrote:
> > > a long time ago I had agreed with Dan
f PSR on such platforms), it doesn't enable
it by default.
So I'd like to nudge once more that this patch be merged.
Daniel, any objections?
Kind regards, David Weinehall
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On Tue, Sep 05, 2017 at 02:25:36PM +0100, Chris Wilson wrote:
> Quoting David Weinehall (2017-09-05 14:10:50)
> > Currently we're doing:
> >
> > 1. acquire lock
> > 2. write word to hardware
> > 3. release lock
> > 4. repeat from 1
> >
> >
n of the patch...
v4: Don't acquire the uncore lock. Disable preempt. (Chris)
Signed-off-by: David Weinehall
---
drivers/gpu/drm/i915/intel_csr.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
On Mon, Sep 04, 2017 at 08:15:57PM +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2017-09-04 20:14:32)
> > Quoting David Weinehall (2017-09-04 20:08:06)
> > > Currently we're doing:
> > >
> > > 1. acquire lock
> > > 2. write word to har
On Mon, Sep 04, 2017 at 07:55:56PM +0100, Chris Wilson wrote:
> Quoting David Weinehall (2017-09-04 19:38:04)
> > v2: Per feedback from Chris & Ville there's no need to do the whole
> > forcewake dance, so lose that bit (Chris, Ville)
>
> > @@ -251,9 +253,
n of the patch...
Signed-off-by: David Weinehall
---
drivers/gpu/drm/i915/intel_csr.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 965988f79a55..28ea24932ef1 100644
--- a/drivers/gpu/drm/i915/int
ntire firmware,
then releases the lock. Testing shows resume speedups
in the order of 10ms on platforms with DMC firmware (GEN9+).
v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)
Signed-off-by: David Weinehall
--
ntire firmware,
then releases the lock. Testing shows resume speedups
in the order of 10ms on platforms with DMC firmware (GEN9+).
Signed-off-by: David Weinehall
---
drivers/gpu/drm/i915/intel_csr.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gp
On Wed, Aug 23, 2017 at 04:03:44PM +0100, Chris Wilson wrote:
> Quoting David Weinehall (2017-08-23 15:54:13)
> > On Fri, Aug 18, 2017 at 03:08:15PM +0100, Chris Wilson wrote:
> > > During suspend we want to flush out all active contexts and their
> > > rendering. To do
ed up that switch bump the GPU clocks.
>
> Switching to the kernel context prior to idling is also used to enforce
> a barrier before changing OA properties, and when evicting active
> rendering from the global GTT. All cases where we do want to
> race-to-idle.
>
> Signed-off-b
bump the GPU clocks.
> >> > >
> >> > > Switching to the kernel context prior to idling is also used to enforce
> >> > > a barrier before changing OA properties, and when evicting active
> >> > > rendering from the global GTT. All
e
if there's something Broxton-related info on PSR in Bspec I missed,
or if it's just our BXT-P RVP that's buggy.
Kind regards, David
> Cheers,
> Rodrigo.
>
>
> On Tue, Aug 8, 2017 at 3:09 AM, David Weinehall
> wrote:
> > While testing Jim Bride's lates
On Tue, Aug 08, 2017 at 10:34:46AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Add has_psr-flag to gen9lp
> URL : https://patchwork.freedesktop.org/series/28488/
> State : failure
>
> == Summary ==
>
> Series 28488v1 drm/i915: Add has_psr-flag to gen9lp
> https://patch
While testing Jim Bride's latest batch of PSR patches I noticed
that gen9lp doesn't include the has_psr flag, and that our GLK
system thus reported PSR as unsupported.
This patch simply adds has_psr.
Signed-off-by: David Weinehall
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file
On Thu, Aug 03, 2017 at 01:43:39PM +0200, Daniel Vetter wrote:
> pm_rpm is one of the main offenders for long runtime in our full igt
> run. And hey, there's a quick option already, so make it the default.
>
> This means there's yet another way to enable stress tests, we really
> need to standardi
v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
> > the hang issue is originally reported) to avoid rare hangs (David)
> >
> > Cc: David Weinehall
> > Reviewed-by: David Weinehall
> > Signed-off-by: Praveen Paneri
> > ---
> > driv
panels whose setup time at the preferred mode is too long.
> With this patch we allow the use of the alternate mode if it's
> available and it was specifically requested.
>
> v2 and v3: Rebase
> v4: * Fix up some leaky mode stuff (Chris)
> * Rebase
> v5: * Fix a NUL
On Sat, Jul 29, 2017 at 10:29:00AM +0530, Praveen Paneri wrote:
> This WA is required when decopled frequencies for slice
> and unslice are enabled. This disables DOP clock gating
> for SKL GT4.
>
> Cc: David Weinehall
> Signed-off-by: Praveen Paneri
Tested to fix hangs on GT
On 2017-08-02 02:15, Pandiyan, Dhinakaran wrote:
On Mon, 2017-07-31 at 15:41 -0700, Puthikorn Voravootivat wrote:
But now you're suggesting another arbitrary narrow selection of panels
based on limited evidence.
I understand your point that the panel I observe is not the
representative of the
rsions? As mentioned elsewhere I experienced issues with both your
previous patch series and the two before that one.
I'll run a new testrun with this series just in case (it might be that
the issues I noticed were caused by bad interaction with some other
component).
Kind regards, David Wein
Squelch reset messages during selftests")
> Signed-off-by: Chris Wilson
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/
On Tue, Jul 25, 2017 at 03:41:46PM +0300, David Weinehall wrote:
> On 2017-07-25 02:15, Puthikorn Voravootivat wrote:
> > I saw a DP 1.3 panel that advertise AUX backlight brightness control
> > but not working properly. So it should work but not in real world.
> > I thin
On 2017-07-25 02:15, Puthikorn Voravootivat wrote:
I saw a DP 1.3 panel that advertise AUX backlight brightness control
but not working properly. So it should work but not in real world.
I think that is good reason enough to add this as a heuristic.
Either key it on eDP 1.4 and hope that it's
On 2017-07-20 12:33, Jani Nikula wrote:
On Wed, 19 Jul 2017, "Pandiyan, Dhinakaran"
wrote:
On Wed, 2017-07-19 at 15:59 +0530, Jenny TC wrote:
With older panels, AUX pin for backlight doesn't work.
What evidence do you have to back up that claim?
Chapter 10.1 does, at least according to my re
> +
> /* Panel supports regional backlight brightness adjustment */
> if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_GENERAL_CAP_3,
> ®_val) != 1) {
>
> On Mon, Jul 10, 2017 at 7:23 AM, David Weinehall
> wrote:
> > This rever
On Mon, Jul 10, 2017 at 02:25:39PM -, Patchwork wrote:
> == Series Details ==
>
> Series: Revert "drm/i915: Add heuristic to determine better way to adjust
> brightness"
> URL : https://patchwork.freedesktop.org/series/27065/
> State : failure
OK, seems I botched that one :S
Will geerate
x27;s premature to enable DPCD backlight
even if the platforms support it).
Signed-off-by: David Weinehall
---
drivers/gpu/drm/i915/i915_params.c| 7 ++-
drivers/gpu/drm/i915/i915_params.h| 1 -
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 61 ++---
On Thu, Jul 06, 2017 at 01:41:13PM -0700, Rodrigo Vivi wrote:
> Apparently no change on RPS stuff from previous platforms.
>
> v2: Merging to rps related patches in one and also adding
> missed cases.
>
> Cc: David Weinehall
> Signed-off-by: Rodrigo Vivi
Double-checki
On Wed, Jul 05, 2017 at 05:40:19PM +0300, David Weinehall wrote:
> On Wed, Jul 05, 2017 at 01:03:46PM +0300, Jani Nikula wrote:
> > On Tue, 04 Jul 2017, David Weinehall
> > wrote:
> > > This reverts commit ae25eceab616d16a07bcaa434b84463d58a3bdc3.
> > >
On Wed, Jul 05, 2017 at 01:03:46PM +0300, Jani Nikula wrote:
> On Tue, 04 Jul 2017, David Weinehall wrote:
> > This reverts commit ae25eceab616d16a07bcaa434b84463d58a3bdc3.
> >
> > The introduction of dynamic backlight control causes
> > Lenovo ThinkPad X1 Carbon 4th Ge
This reverts commit ae25eceab616d16a07bcaa434b84463d58a3bdc3.
The introduction of dynamic backlight control causes
Lenovo ThinkPad X1 Carbon 4th Gen to boot to a black screen;
presumably the backlight is off.
Signed-off-by: David Weinehall
---
drivers/gpu/drm/i915/i915_params.c| 5
On Mon, Jul 03, 2017 at 08:41:53PM +0530, Shashank Sharma wrote:
> CEA-861-F introduces extended tag codes for EDID extension blocks,
> which indicates the actual type of the data block. The code for
> using exteded tag is 0x7, whereas in the existing code, the
> corresponding macro is named as "VI
On Mon, Jun 26, 2017 at 04:40:08PM -0400, Lyude wrote:
> There's quite a number of machines on the market, mainly Lenovo
> ThinkPads, that make the horrible mistake in their firmware of reusing
> the PCIBAR space reserved for the SMBus for things that are completely
> unrelated to the SMBus control
On Tue, Jun 27, 2017 at 10:29:33PM +, Pandiyan, Dhinakaran wrote:
>
>
>
> On Tue, 2017-06-27 at 16:23 +0300, David Weinehall wrote:
> > On Mon, Jun 26, 2017 at 05:18:19PM +0300, David Weinehall wrote:
> > > On Thu, Jun 22, 2017 at 12:03:39PM -0700, Puthikorn Vorav
i915_gem_suspend() improves S3 latency
> by about 30ms on Skylake (ymmv).
>
> Reported-by: David Weinehall
> Signed-off-by: Chris Wilson
> Cc: David Weinehall
Tested-by: David Weinehall
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/i915_gem.c | 2 --
> 1
On Mon, Jun 26, 2017 at 05:18:19PM +0300, David Weinehall wrote:
> On Thu, Jun 22, 2017 at 12:03:39PM -0700, Puthikorn Voravootivat wrote:
> > This patch adds option to enable dynamic backlight for eDP
> > panel that supports this feature via DPCD register and
> > set minimum
On Mon, Jun 12, 2017 at 08:54:02PM +0530, Animesh Manna wrote:
> Along with below patches sharing some background details/design.
> - On BXT, Display cannot generate an interrupt when in D3.
> - Without display in D3, S0ix can be achieved, Power impact will be zero if
> d3 is blocked. PMCSR for Gr
On Thu, Jun 22, 2017 at 12:03:39PM -0700, Puthikorn Voravootivat wrote:
> This patch adds option to enable dynamic backlight for eDP
> panel that supports this feature via DPCD register and
> set minimum / maximum brightness to 0% and 100% of the
> normal brightness.
This patch causes a regression
object is a much better definition of the minimum
> caching level.
>
> Fixes: 3bbaba0ceaa2 ("drm/i915: Added Programming of the MOCS")
> Signed-off-by: Chris Wilson
> Cc: David Weinehall
> Cc: Arkadiusz Hiler
> Cc: Tvrtko Ursulin
> Cc: sta...@vger.kernel.or
On Thu, May 04, 2017 at 10:35:33AM +0200, Arkadiusz Hiler wrote:
> On Thu, Apr 27, 2017 at 05:23:16PM +0100, Chris Wilson wrote:
> > On Thu, Apr 27, 2017 at 06:30:42PM +0300, David Weinehall wrote:
> > > On Thu, Apr 27, 2017 at 04:55:20PM +0200, Arkadiusz Hiler wrote:
> >
On Thu, Apr 27, 2017 at 04:55:20PM +0200, Arkadiusz Hiler wrote:
> On Wed, Apr 26, 2017 at 06:00:41PM +0300, David Weinehall wrote:
> > Add a bunch of MOCS entries for gen 9 that were missing from intel_mocs.
> > Some of these are used by media-sdk; if these entries are missing
use in our nightly
testing, without regressing any other benchmarks.
Signed-off-by: David Weinehall
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index 92e461c68385..5236a442a14f 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915
On 2017-04-05 18:46, Kamble, Sagar A wrote:
On 4/5/2017 6:32 PM, David Weinehall wrote:
On 2017-04-05 15:54, Joonas Lahtinen wrote:
On ke, 2017-04-05 at 15:51 +0530, Sagar Arun Kamble wrote:
i915 is currently doing Full GPU reset at the end of suspend
followed by
GuC suspend. This reset
On 2017-04-05 15:54, Joonas Lahtinen wrote:
On ke, 2017-04-05 at 15:51 +0530, Sagar Arun Kamble wrote:
i915 is currently doing Full GPU reset at the end of suspend followed by
GuC suspend. This reset bypasses the GuC. We need to tell the GuC to
suspend before we do a direct intel_gpu_reset, Othe
On Wed, Mar 22, 2017 at 12:53:24PM +0200, Jani Nikula wrote:
> On Wed, 22 Mar 2017, David Weinehall wrote:
> > rm -rf / woes can be remedied by always passing "--preserve-root" to rm
> > (I believe that this is the default already though).
>
> That doesn't
On Tue, Mar 21, 2017 at 01:50:48PM +0100, Daniel Vetter wrote:
> On Tue, Mar 21, 2017 at 01:15:59PM +0200, Jani Nikula wrote:
> > On Tue, 21 Mar 2017, Daniel Vetter wrote:
> > > On Tue, Mar 21, 2017 at 12:14:31PM +0200, Jani Nikula wrote:
> > >> Fix shellcheck SC2115: Use "${var:?}" to ensure this
On Sun, Mar 12, 2017 at 01:21:12PM +, Chris Wilson wrote:
> On Fri, Mar 10, 2017 at 05:14:32PM -0800, Kenneth Graunke wrote:
> > On systems without LLC, drm_intel_gem_bo_map_unsynchronized() has
> > had the surprising behavior of doing a synchronized GTT mapping.
> > This is obviously not what
e clutter in
> intel_prepare_dp_ddi_buffers(), and we'll have other uses for some
> of these new helper functions later on.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 126
> +++
> 1 fil
are defined. To that end we introduce
> intel_ddi_dp_voltage_max() which will actually look at the proper
> translation table to determine what is the maximum voltage swing level
> supported.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: David Weinehall
> ---
&g
other uses for this table later on.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 60
> ++--
> 1 file changed, 21 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/dr
On Fri, Feb 17, 2017 at 11:22:04AM -0200, Paulo Zanoni wrote:
> The functions are pretty much the same, except for the CDCLK and VCO
> calculations. Add BDW support to vlv_modeset_calc_cdclk() and add
> BXT/GLK support to skl_modeset_calc_cdclk(). The two reamining
s/reamining/remaining/
> functi
On Wed, Feb 15, 2017 at 09:34:23AM -0800, Rodrigo Vivi wrote:
> There is a new version of DMC available for Kabylake.
s/Kabylake/Gemini Lake/
>
> It's release notes only mention:
> - Enhancement in the FW to restore the PG2 state
>
> v2: cook on top of drm-tip without depending on kbl one so CI
causes enable
> timeouts in Geminilake.
>
> Cc: David Weinehall
> Signed-off-by: Ander Conselvan de Oliveira
>
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +++
> drivers/gpu/drm/i915/intel_ddi.c| 49
&
gt; i915_pm_resume+0xe/0x10 [i915]
> pci_pm_resume+0x64/0xa0
> dpm_run_callback+0xa1/0x2a0
> ? pci_pm_thaw+0x90/0x90
> device_resume+0xe3/0x200
> async_resume+0x1d/0x50
> async_run_entry_fn+0x39/0x170
> process_one_work+0x212/0x670
> ? process_one_work+0x197/0x670
> worker
ind a testcase in i-g-t that easily reproduces the issue
that'd also be very helpful. Do note that not all testcases in i-g-t
are run as part of our nightly tests, since some of them are *extremely*
time consuming; the full combinatorial testcase, for instance, can
take weeks or months--I haven&
se.
> Cc: David Weinehall
> Cc: Rodrigo Vivi
> Signed-off-by: Ander Conselvan de Oliveira
>
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
> drivers/gpu/drm/i915/intel_lrc.c| 6 +++---
> drivers/gpu/drm/i915/intel_mocs.
On Thu, Jan 12, 2017 at 01:47:37PM +0200, Ander Conselvan de Oliveira wrote:
> Apply workarounds to Geminilake, and annoatate those that are applied
annotate
> uncondionally when they apply to GLK based on the workaround database.
unconditionally
>
> Signed-off-by: Ander Conselvan de Oliveira
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