rupts")
Fixes: 54c52a841250 ("drm/i915/guc: Correctly handle GuC interrupts on Gen11")
Fixes: 2ae096872a2c ("drm/i915/pxp: Implement PXP irq handler")
Fixes: 3e7abf814193 ("drm/i915: Extract GT render power state management")
Signed-off-by: Zhanjun Dong
---
Cc: Ala
("drm/i915/guc: Update GuC debugfs to support new GuC")
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Matthew Brost
Cc: # v5.15+
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 20 +--
1 file changed, 14 insertions(+), 6
e GuC debugfs to support new GuC")
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Matthew Brost
---
I believe this should fix issue #13343, but I wasn't able to repro
the bug to confirm that it is indeed gone with this change.
.../gpu/drm/i915/gt/uc/intel_guc_su
On 12/24/2024 10:13 AM, John Harrison wrote:
On 12/23/2024 15:20, Daniele Ceraolo Spurio wrote:
On 12/20/2024 5:19 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Add debug info to help investigate a very rare bug:
https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13385
On 12/20/2024 5:19 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Add debug info to help investigate a very rare bug:
https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13385
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 3 +++
1 file
while still catching any initialization failures, we lose the
actual returned error code. This can be easily improved by checking the
status value and printing it to dmesg if it's an error.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_
state.
Add the missing tasklet flush to flush all 3 parts.
Signed-off-by: Zhanjun Dong
Cc: John Harrison
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submissio
On 11/4/2024 3:02 PM, John Harrison wrote:
On 10/28/2024 16:31, Daniele Ceraolo Spurio wrote:
All MTL and ARL SKUs share the same GSC FW, but the newer platforms are
only supported in newer blobs. In particular, ARL-S is supported
starting from 102.0.10.1878 (which is already the minimum
. Therefore, the driver needs to check which specific ARL
subplatform its running on when verifying that the GSC FW is new enough
for it.
Fixes: 2955ae8186c8 ("drm/i915: ARL requires a newer GSC firmware")
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Rodrigo Vivi
---
drivers/gp
On 10/24/2024 6:21 PM, Kandpal, Suraj wrote:
-Original Message-
From: Ceraolo Spurio, Daniele
Sent: Thursday, October 24, 2024 9:03 PM
To: Kandpal, Suraj ; intel...@lists.freedesktop.org;
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K ; Ghimiray, Himal Prasad
Subject: Re: [
On 10/22/2024 12:29 AM, Suraj Kandpal wrote:
Add check to remove HDCP2 compatibility from BMG as it does not
have GSC which ends up causing warning when we try to get reference
of GSC FW.
Fixes: 89d030804831 ("drm/xe/hdcp: Fix condition for hdcp gsc cs requirement")
Fixes: 883631771038 ("drm
ch to test a specific FW release, instead
of updating the macros we can just hardcode the path.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw
On 8/20/2024 3:28 PM, Cavitt, Jonathan wrote:
-Original Message-
From: Intel-gfx On Behalf Of Daniele
Ceraolo Spurio
Sent: Tuesday, August 20, 2024 3:00 PM
To: intel-gfx@lists.freedesktop.org
Cc: Ceraolo Spurio, Daniele ; Teres Alexis, Alan Previn
; Harrison, John C ; Vivi
also fixed by not
attempting to load the GSC FW after an error.
Fixes: 15bd4a67e914 ("drm/i915/gsc: GSC firmware loading")
Signed-off-by: Daniele Ceraolo Spurio
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/uc/int
the fixes tag added:
Reviewed-by: Daniele Ceraolo Spurio
However, given that this is a non-backward compatible change that we'd
be propagating as a fix, please get a maintainer ack as well. IMO there
should be no problem since this is only breaking for ARL and that
platform hasn'
08-01 11:11:04 -0700)
------------
Daniele Ceraolo Spurio (5):
i915: update DG2 HuC to v7.10.16
xe: Add LNL HuC 9.4.13
xe: Add GSC 104.0.0.1161 for LNL
xe: Add BMG HuC 8.2.10
i915: update MTL GSC to v102.0.10.1878
Dnyaneshwar Bhadane (1):
i915: Update MTL DMC v2.22
Julia Filip
On 6/5/2024 5:17 PM, Andi Shyti wrote:
The ce->guc_state.lock was made to protect guc_prio, which
indicates the GuC priority level.
But at the begnning of the function we perform some sanity check
of guc_prio outside its protected section. Move them within the
locked region.
Use this occasio
Ooops, wrong mailing list, please ignore. I'll re-send it to intel-xe.
Daniele
On 4/15/2024 4:17 PM, Daniele Ceraolo Spurio wrote:
The flow is the same as MTL, so the only things we need to add are the
GSCCS and FW definitions.
Due to the FW not being in its final state yet, we can'
links in
if we decide to go with the series as-is.
Cc: Lucas De Marchi
Daniele Ceraolo Spurio (3):
drm/xe/gsc: define GSCCS for LNL
drm/xe/gsc: Skip GSC proxy init
drm/xe/gsc: define GSC FW for LNL
drivers/gpu/drm/xe/xe_gsc_proxy.c | 9 +
drivers/gpu/drm/xe/xe_pci.c | 3 +
The mei support for LNL hasn't landed yet, so we can't use the GSC proxy
component. Note that the lack of the GSC proxy means that the content
protection features (PXP, HDCP) won't work.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/xe/xe_gsc_proxy.c | 9 +
1
Interface and compatibility versions are the same as MTL.
Note that the FW is still in development and the current release is
for CI only. Theefore, we'll need to keep this patch in the xe-for-ci
branch until we get the finalized FW release.
Signed-off-by: Daniele Ceraolo Spurio
---
dr
LNL has 1 GSCCS, same as MTL. Note that the GSCCS will be disabled until
we have a GSC FW defined, but having it in the list of engine is a
requirement to add such definition.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/xe/xe_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1
: Daniele Ceraolo Spurio
Cc: John Harrison
---
.../gpu/drm/i915/selftests/i915_selftest.c| 36 ---
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_selftest.c
b/drivers/gpu/drm/i915/selftests/i915_selftest.c
index ee79e0809a6d
to fetch changes up to ab144168469a77f54ad539ac98dede7ce4c6a75d:
i915: Add DG2 HuC 7.10.15 (2024-03-28 13:45:41 -0700)
------------
Daniele Ceraolo Spurio (1):
i915: Add DG2 HuC 7.10.15
WHENCE | 2 +-
i915/dg2_huc_
This is to test the new HuC release before overwriting the existing one.
This patch is for testing only and it should not be merged.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
On 2/13/2024 9:33 PM, Kandpal, Suraj wrote:
interaction of HDCP as a client with the GSC CS interface.
--v2
-add kfree at appropriate place [Daniele] -remove useless define
[Daniele] -move host session logic to xe_gsc_submit.c [Daniele] -call
xe_gsc_check_and_update_pending directly in an if
On 2/9/2024 2:14 AM, Suraj Kandpal wrote:
Enable HDCP for Xe by defining functions which take care of
interaction of HDCP as a client with the GSC CS interface.
--v2
-add kfree at appropriate place [Daniele]
-remove useless define [Daniele]
-move host session logic to xe_gsc_submit.c [Daniele
uc.gsc.fw))
return false;
With this change:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+ xe_pm_runtime_get(xe);
+ ret = xe_force_wake_get(gt_to_fw(gt), XE_FW_GSC);
+ if (ret) {
+ drm_dbg_kms(&xe->drm,
+ "failed
On 2/9/2024 2:14 AM, Suraj Kandpal wrote:
Use xe_device struct instead of drm_i915_private so as to not
cause confusion and comply with Xe standards even though xe_device
gets translated to drm_i915_private.
AFAIU xe_device does not get translated to drm_i915_private, it's really
an xe_devi
On 2/7/2024 3:35 AM, Suraj Kandpal wrote:
Enable HDCP for Xe by defining functions which take care of
interaction of HDCP as a client with the GSC CS interface.
--v2
-add kfree at appropriate place [Daniele]
-forward declare drm_i915_private [Daniele]
I don't see the forward declaration, ju
On 2/7/2024 3:35 AM, Suraj Kandpal wrote:
Expose gsc_proxy_init_done so that we can check if gsc proxy has
been initialized or not.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 25 ++--
drivers/gpu/drm/xe/xe_gsc_proxy.c| 2 +-
d
On 2/6/2024 8:24 AM, Kandpal, Suraj wrote:
Subject: Re: [PATCH 2/3] drm/xe/hdcp: Enable HDCP for XE
On 2/2/2024 12:37 AM, Suraj Kandpal wrote:
Enable HDCP for Xe by defining functions which take care of
interaction of HDCP as a client with the GSC CS interface.
Signed-off-by: Suraj Kandpa
On 2/2/2024 12:37 AM, Suraj Kandpal wrote:
Enable HDCP for Xe by defining functions which take care of
interaction of HDCP as a client with the GSC CS interface.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 188 ++-
1 file changed, 184 in
e
board
+* really should never get that hot in real life!). IFWI issues have
been
+ * seen to cause sporadic failures to grant the higher frequency. And at
+* minimum frequency, the load time can be in the seconds range. Note
that
this is not load time but auth time. Wi
epare, so there is a chance
that it might run parallel to the reset/wedge code, which we handle by
checking the submission status. The list manipulation is protected by
spinlock so we're safe on that side. The rest of the approach also LGTM:
Acked-by: Daniele Ceraolo Spurio
Daniele
i
class")
Reported-by: Alan Previn Teres Alexis
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 5 +++--
drivers/gpu/drm/i915/i915_gpu_error.h
working.
v2: Fix some dumb over-complications and a couple of typos - review
feedback from Daniele.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 9 ++
drivers/gpu
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: Matt Roper
Reviewed-by: Daniele Ceraolo Spurio # v1
My r-b stands.
Thanks,
Daniele
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 39 -
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/dri
in the state tracking.
Prevent that by checking the pending enable flag before trying to
enable a context.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
ss is automatically correctly
assigned.
Engine will show as 65535:0 other0 in the logs/traces which should
be unique enough.
Signed-off-by: Tvrtko Ursulin
Fixes: 194babe26bdc ("drm/i915/mtl: don't expose GSC command streamer to the
user")
Cc: Daniele Ceraolo Spurio
Cc: Alan Pr
On 11/14/2023 9:20 AM, Tvrtko Ursulin wrote:
On 14/11/2023 17:03, Daniele Ceraolo Spurio wrote:
On 11/13/2023 8:46 AM, Tvrtko Ursulin wrote:
On 13/11/2023 15:51, Daniele Ceraolo Spurio wrote:
On 11/10/2023 4:00 AM, Tvrtko Ursulin wrote:
On 09/11/2023 23:53, Daniele Ceraolo Spurio wrote
On 11/13/2023 8:46 AM, Tvrtko Ursulin wrote:
On 13/11/2023 15:51, Daniele Ceraolo Spurio wrote:
On 11/10/2023 4:00 AM, Tvrtko Ursulin wrote:
On 09/11/2023 23:53, Daniele Ceraolo Spurio wrote:
The GSC CS is not exposed to the user, so we skipped assigning a uabi
class number for it
On 11/10/2023 4:00 AM, Tvrtko Ursulin wrote:
On 09/11/2023 23:53, Daniele Ceraolo Spurio wrote:
The GSC CS is not exposed to the user, so we skipped assigning a uabi
class number for it. However, the trace logs use the uabi class and
instance to identify the engine, so leaving uabi class
On 11/9/2023 6:06 PM, John Harrison wrote:
On 11/9/2023 15:54, Daniele Ceraolo Spurio wrote:
On MTL, the HuC is only supported on the media GT, so our validation
check on the module parameter detects an inconsistency on the root GT
(the modparams asks to enable HuC, but the support is not
y see a message about GuC not being supported, so instead of just
silencing the HuC message on newer platforms we can just get rid of it
entirely.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 5 -
1 file changed, 5 deletions(-)
diff --gi
, we can't add a new
case in the uabi enum, so we insted internally define a kernel
reserved class using the next free number.
Fixes: 194babe26bdc ("drm/i915/mtl: don't expose GSC command streamer to the
user")
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: A
pre-emptible. That way the heartbeat can get
through if the GuC is alive and context switching. Thus a reset only
happens if the GuC dies. Thus, if the kill should stop working the
test will now fail rather than claim to pass.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
On 11/6/2023 3:59 PM, john.c.harri...@intel.com wrote:
From: John Harrison
There is a mechanism for reporting errors from fire and forget H2G
messages. This is the only way to find out about almost any error in
the GuC backend submission path. So it would be useful to know that it
is working
you to fetch changes up to ca4d55fbc3feca49f097afc86bbdfe88a8aa82d9:
xe: add PVC GUC 70.9.1 (2023-10-04 09:31:44 -0700)
------------
Daniele Ceraolo Spurio (1):
xe: add PVC GUC 70.9.1
WHENCE| 8
xe/pvc_gu
/drm/intel/-/issues/7077
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 38 +--
1 file changed,
On 9/11/2023 5:52 PM, Umesh Nerlige Ramappa wrote:
The worker is canceled in the __gt_park path, but we still see it
running sometimes during suspend.
Only update stats if gt is awake. If not, intel_guc_busyness_park would
have already updated the stats. Note that we do not requeue the worker
fetch changes up to a5dbe400f776b0dc2d0a402ba76b4c16c231b38e:
i915: update MTL HuC to version 8.5.4 (2023-09-14 08:34:08 -0700)
------------
Daniele Ceraolo Spurio (1):
i915: update MTL HuC to version 8.5.4
WHENCE | 2 +-
i915/mtl_huc_
On 9/8/2023 10:16 PM, Umesh Nerlige Ramappa wrote:
The worker is canceled in the __gt_park path, but we still see it
running sometimes during suspend. This is likely because some code is
getting a gt wakeref in the __gt_park path.
This possible root-cause doesn't seem plausible to me, because a
fetch changes up to 82ef648d026200e40a597ba7ea795b1c97dcebf2:
i915: update MTL HuC to version 8.5.4 (2023-09-06 13:58:22 -0700)
------------
Daniele Ceraolo Spurio (1):
i915: update MTL HuC to version 8.5.4
WHENCE | 2 +-
i915/mtl_huc_
names.
Same as with the GuC, a major version bump indicate a
backward-incompatible change, while a minor version bump indicates a
backward-compatible one, so we use only the former in the file name.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Cc: Tvrtko Ursulin
Cc
5
for you to fetch changes up to 81caac98eda1696fa057191ee969c377154a:
i915: add GSC 102.0.0.1655 for MTL (2023-08-21 14:13:11 -0700)
--------
Daniele Ceraolo Spurio (1):
i915: add GSC 102.0.0.1655 for MTL
WHENCE
5
for you to fetch changes up to 81caac98eda1696fa057191ee969c377154a:
i915: add GSC 102.0.0.1655 for MTL (2023-08-21 14:13:11 -0700)
--------
Daniele Ceraolo Spurio (1):
i915: add GSC 102.0.0.1655 for MTL
WHENCE
).
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7061
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Andi Shyti #v1
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/g
git://anongit.freedesktop.org/drm/drm-firmware xe_pvc
for you to fetch changes up to 3b72a71413f8ef76c76e1dbff0273ac3b77f68da:
xe: add PVC guc 70.6.4 and 70.8.0 (2023-07-31 14:16:51 -0700)
----
Daniele Ceraolo Spurio (1):
xe: add PVC
p to 3b72a71413f8ef76c76e1dbff0273ac3b77f68da:
xe: add PVC guc 70.6.4 and 70.8.0 (2023-07-31 14:16:51 -0700)
----
Daniele Ceraolo Spurio (1):
xe: add PVC guc 70.6.4 and 70.8.0
WHENCE| 11 +++
xe/pvc_guc_70.6.4.bin | B
u to fetch changes up to 2a1f9984c8485eb56cb3825101a374750a8244f9:
i915: add GSC 102.0.0.1636 for MTL (2023-07-21 10:02:39 -0700)
--------
Daniele Ceraolo Spurio (1):
i915: add GSC 102.0.0.1636 for MTL
WHENCE | 3
off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 1ce07d7e8769..88215b5efe72 100644
--- a/drivers/g
for you to fetch changes up to 6f3a37f47d68d5e2108b98a900e4be910e8c7106:
i915: update DG2 GuC to v70.8.0 (2023-07-20 10:14:57 -0700)
--------
Daniele Ceraolo Spurio (2):
i915: update to GuC 70.8.0 and HuC 8.5.1 for MTL
i915: update
-07-19 11:05:35 -0700)
--------
Daniele Ceraolo Spurio (3):
i915: update to GuC 70.8.0 and HuC 8.5.1 for MTL
i915: add GSC 102.0.0.1625 for MTL
i915: update DG2 GuC to v70.8.0
WHENCE | 9 ++---
i915/dg2_gu
e can print an error message and abort HuC loading if the binaries are
out of sync instead of failing the authentication.
v2: Add clarification comment, fix typo in commit msg, clean up variable
declaration (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Reviewed-by: Andrzej Hajda
for you to fetch changes up to e372271d839f921a147c03d10e8fd882a34c4890:
i915: add GSC 102.0.0.1625 for MTL (2023-07-17 10:47:13 -0700)
--------
Daniele Ceraolo Spurio (1):
i915: add GSC 102.0.0.1625 for MTL
WHENCE | 3
u to fetch changes up to 1e7fa2cfef80974642bfbaefc11e59e54244164a:
i915: update DG2 GuC to v70.8.0 (2023-07-14 13:55:31 -0700)
--------
Daniele Ceraolo Spurio (1):
i915: update DG2 GuC to v70.8.0
WHENCE | 2 +-
i915/dg2_
e can print an error message and abort HuC loading if the binaries are
out of sync instead of failing the authentication.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 42
1 file changed, 42 insertions(+)
diff --
1
for you to fetch changes up to e05f81327fdf25f8c5508afdc1b0d3e2862a1663:
i915: update to GuC 70.8.0 and HuC 8.5.1 for MTL (2023-07-11 12:01:10 -0700)
--------
Daniele Ceraolo Spurio (1):
i915: update to GuC 70.8.0 and HuC 8.5
ff-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 32 ++--
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/dr
o which
is success instead of failure.
Fix this by adding the missing error code when VMA allocation fails.
Fixes: 08872cb13a71 ("drm/i915/mtl/huc: auth HuC via GSC")
Signed-off-by: Harshit Mogalapalli
Reviewed-by: Daniele Ceraolo Spurio
---
Re-sending for testing, because it looks like
names.
Same as with the GuC, a major version bump indicate a
backward-incompatible change, while a minor version bump indicates a
backward-compatible one, so we use only the former in the file name.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan
owns the GSC).
To make it simpler to loop through the status register, the code has
been update to use a PICK macro and the existing code using the regs had
been adapted to match.
v2: fix includes and copyright dates (Alan)
v3: actually fix the includes
Signed-off-by: Daniele Ceraolo Spurio
Cc
ed to navigate through various headers in
the binary. See in-code comment for details.
v2: fix and improve size checks when crawling the binary header, add
comment about the different version, wrap the partition base/offset
pairs in the GSC header in a struct (Alan)
Signed-off-by: Daniele Ceraolo Spuri
size (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 95 ++-
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 50
cause that's the default setting for stolen memory on !LLC
platforms.
v2: only memset the memory we're not overwriting (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Cc: Vinay Belgaumkar
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/inte
efore merging.
Daniele Ceraolo Spurio (4):
drm/i915/gsc: fixes and updates for GSC memory allocation
drm/i915/mtl/gsc: extract release and security versions from the gsc
binary
drm/i915/mtl/gsc: query the GSC FW for its compatibility version
drm/i915/mtl/gsc: Add a gsc_info debugfs
driver
u to fetch changes up to 5de33fb45cee8d83abfe17e9e85bd74d51a2653f:
i915: Add HuC v8.5.0 for MTL (2023-06-06 09:24:40 -0700)
--------
Daniele Ceraolo Spurio (1):
i915: Add HuC v8.5.0 for MTL
WHENCE | 3 +++
i915/mtl_h
owns the GSC).
To make it simpler to loop through the status register, the code has
been update to use a PICK macro and the existing code using the regs had
been adapted to match.
v2: fix includes and copyright dates (Alan)
v3: actually fix the includes
Signed-off-by: Daniele Ceraolo Spurio
Cc
names.
Same as with the GuC, a major version bump indicate a
backward-incompatible change, while a minor version bump indicates a
backward-compatible one, so we use only the former in the file name.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan
size (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn #v1
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 95 ++-
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 50
owns the GSC).
To make it simpler to loop through the status register, the code has
been update to use a PICK macro and the existing code using the regs had
been adapted to match.
v2: fix includes and copyright dates (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John
ed to navigate through various headers in
the binary. See in-code comment for details.
v2: fix and improve size checks when crawling the binary header, add
comment about the different version, wrap the partition base/offset
pairs in the GSC header in a struct (Alan)
Signed-off-by: Daniele Ceraolo Spuri
: fix header parsing, address other minor review comments.
Cc: Alan Previn
Cc: John Harrison
Cc: Suraj Kandpal
Daniele Ceraolo Spurio (5):
drm/i915/gsc: fixes and updates for GSC memory allocation
drm/i915/mtl/gsc: extract release and security versions from the gsc
binary
drm/i915/mt
cause that's the default setting for stolen memory on !LLC
platforms.
v2: only memset the memory we're not overwriting (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Cc: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 29 ++---
drive
Follow the same logic as DG2, so just a meu binary with no version number.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
to explain the
different approaches to load and auth (John)
v4: update call to intel_huc_is_authenticated in the pxp code to check
for GSC authentication
v5: drop references to meu and esclamation mark in huc_auth print (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John
has completed before
proceding with the full auth
v3: use a define for the object size (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 27 +-
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 2 +-
drivers/gpu/drm/i915/gt/uc
On MTL, for obvious reasons, HuC is only available on the media tile.
We already disable SW support for HuC on the root gt due to the
absence of VCS engines, but we also need to update the getparam to point
to the HuC struct in the media GT.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John
/is_meu_binary/has_gsc_headers/, clearer logs (John)
v3: split check for GSC access, better comments (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 49 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.h
e pinning in an area that was previously reserved for
thus purpose), we do need to explicitly re-pin on resume because the
automated helper won't cover us.
v2: better comments and commit message, s/dummy/vma_res/
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harriso
e commit
message, check ccs validity, drop old version location defines.
v3: drop references to the MEU tool to reduce confusion, fix log (John)
v4: fix log for real (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn #v2
---
5: better comments/logs/defines, fix checkpatch issues
Cc: Alan Previn
Cc: John Harrison
Acked-by: Tony Ye
Daniele Ceraolo Spurio (7):
drm/i915/uc: perma-pin firmwares
drm/i915/huc: Parse the GSC-enabled HuC binary
drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so
drm/
explain the
different approaches to load and auth (John)
v4: update call to intel_huc_is_authenticated in the pxp code to check
for GSC authentication
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn #v2
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c
Follow the same logic as DG2, so just a meu binary with no version number.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
e commit
message, check ccs validity, drop old version location defines.
v3: drop references to the MEU tool to reduce confusion, fix log (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn #v2
---
.../drm/i915/gt/uc/intel_gsc_bi
has completed before
proceding with the full auth
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 27 +-
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 50 +++---
drivers
/is_meu_binary/has_gsc_headers/, clearer logs (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 29 ++-
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |
explain the
different approaches to load and auth (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
Reviewed-by: Alan Previn #v2
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 111 --
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 16 +++-
drivers
On MTL, for obvious reasons, HuC is only available on the media tile.
We already disable SW support for HuC on the root gt due to the
absence of VCS engines, but we also need to update the getparam to point
to the HuC struct in the media GT.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John
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