- power1_max
Some non-standard HWMON power information is also provided, such as
enable bits and intervals.
Signed-off-by: Dale B Stimson
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile
- i915_hwmon_init slightly later, after call to i915_setup_sysfs()
- i915_hwmon_fini slightly earlier, before i915_teardown_sysfs()
V2 Fixed some strong typing issues with le32 functions.
Detected by sparse in a run by kernel test robot:
Reported-by: kernel test robot
Dale B Stimson (1)
On 2021-06-01 14:39:11, Sundaresan, Sujaritha wrote:
> Date: Tue, 1 Jun 2021 14:39:11 -0700
> From: "Sundaresan, Sujaritha"
> To: Dale B Stimson ,
> intel-gfx@lists.freedesktop.org, dri-de...@lists.freedesktop.org
> CC: Jon Ewins , Jani Nikula
>
> Subject: Re: [
- power1_max
Some non-standard HWMON power information is also provided, such as
enable bits and intervals.
Signed-off-by: Dale B Stimson
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile
with le32 functions.
Detected by sparse in a run by kernel test robot:
Reported-by: kernel test robot
Dale B Stimson (1):
drm/i915/dg1: Add HWMON power sensor support
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
drivers/gpu/drm/i915/Kconfig |
- power1_max
Some non-standard HWMON power information is also provided, such as
enable bits and intervals.
Signed-off-by: Dale B Stimson
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile
with le32 functions.
Detected by sparse in a run by kernel test robot:
Reported-by: kernel test robot
Dale B Stimson (1):
drm/i915/dg1: Add HWMON power sensor support
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
drivers/gpu/drm/i915/Kconfig |
- power1_max
Some non-standard HWMON power information is also provided, such as
enable bits and intervals.
Signed-off-by: Dale B Stimson
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile
with le32 functions.
Detected by sparse in a run by kernel test robot:
Reported-by: kernel test robot
Dale B Stimson (1):
drm/i915/dg1: Add HWMON power sensor support
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
drivers/gpu/drm/i915/Kconfig |
- power1_max
Some non-standard HWMON power information is also provided, such as
enable bits and intervals.
Signed-off-by: Dale B Stimson
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile
y kernel test robot:
Reported-by: kernel test robot
Dale B Stimson (1):
drm/i915/dg1: Add HWMON power support
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm
On 2021-04-21 18:03:51, Jani Nikula wrote:
> On Tue, 13 Apr 2021, Dale B Stimson wrote:
> > As part of the System Managemenent Interface (SMI), use the HWMON
> > subsystem to display power utilization.
> >
> > The following standard HWMON power sensors are c
ini slightly earlier, before i915_teardown_sysfs()
V2 Fixed some strong typing issues with le32 functions.
Detected by sparse in a run by kernel test robot:
Reported-by: kernel test robot
Dale B Stimson (1):
drm/i915/dg1: Add HWMON power sensor support
drivers/gpu/drm/i915/Kconfig
- power1_max
Some non-standard HWMON power information is also provided, such as
enable bits and intervals.
Signed-off-by: Dale B Stimson
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 9 +
drivers/gpu/drm/i915
- power1_max
Some non-standard HWMON power information is also provided, such as
enable bits and intervals.
Signed-off-by: Dale B Stimson
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 8 +
drivers/gpu/drm/i915
From: Chris Wilson
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Subsequent to sign-off by Chris Wilson, added by Dale B Stimson:
Modify previous &q
Signed-off-by: Dale B Stimson
---
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c | 353 +++
lib/i915/gem_mmio_base.h | 19 +++
lib/igt.h| 1 +
lib/meson.build | 1 +
5 files changed, 376 insertions(+)
create mode
mmio_base from debugfs (if possible)
The availability of sysfs info for mmio_base depends on the presence of
these two proposed kernel patches, not presently merged:
drm/i915/gt: Expose engine properties via sysfs
drm/i915/gt: Expose engine->mmio_base via sysfs
Signed-off-by: Dale B Stim
r with the mmio_base object handle.
Chris Wilson (1):
i915/gem_ctx_isolation: Check engine relative registers (revised)
Dale B Stimson (1):
i915/gem_mmio_base.c - get mmio_base from debugfs (if possible)
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c
From: Chris Wilson
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson
Reviewed-by: Dale B Stimson
---
tests/i
ound for future use?
The 2020-01-27 patches define function gem_engine_mmio_base() with its first
parameter as "fd". The new patches replace the first parameter with the
mmio_base object handle.
Chris Wilson (1):
i915/gem_ctx_isolation: Check engine relative registers
Dale B S
Modify previous i915/gem_ctx_isolation "Check engine relative registers"
for modified mmio_base infrastructure.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 87 +++---
1 file changed, 48 insertions(+), 39 deletions(-)
diff --git a/
Signed-off-by: Dale B Stimson
---
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c | 353 +++
lib/i915/gem_mmio_base.h | 19 +++
lib/igt.h| 1 +
lib/meson.build | 1 +
5 files changed, 376 insertions(+)
create mode
On 2020-02-13 10:29:55, Petri Latvala wrote:
> On Wed, Feb 12, 2020 at 05:28:40PM -0800, Dale B Stimson wrote:
> > At the start of igt_main, failure of the initial tests for successful
> > initialization transfer control to the end of an igt_fixture block.
> > From there, exec
gine entry at index 0, which
had received information describing the last potential engine.
This happened without end.
Signed-off-by: Dale B Stimson
---
lib/i915/gem_engine_topology.c | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git
Modify previous i915/gem_ctx_isolation "Check engine relative registers"
for modified mmio_base infrastructure.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 87 +++---
1 file changed, 48 insertions(+), 39 deletions(-)
diff --git a/
-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 07ffbb84a..b11158dab 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -898
Signed-off-by: Dale B Stimson
---
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c | 353 +++
lib/i915/gem_mmio_base.h | 19 +++
lib/igt.h| 1 +
lib/meson.build | 1 +
5 files changed, 376 insertions(+)
create mode
btest"
- igt_exit() would exit prematurely.
Signed-off-by: Dale B Stimson
---
lib/igt_core.c | 27 +++
lib/igt_core.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 70465130c..78704b93a 100644
--- a/lib/igt_core.c
+++ b/lib/
new patches replace the first parameter with the
mmio_base object handle.
Chris Wilson (1):
i915/gem_ctx_isolation: Check engine relative registers
Dale B Stimson (4):
i915/gem_mmio_base.c - get mmio_base from debugfs (if possible)
i915/gem_ctx_isolation: Check engine relative registe
From: Chris Wilson
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson
Reviewed-by: Dale B Stimson
---
tests/i
My apologies for the multiple submissions of this patch series. I had to
work out an issue with an unsuspected git config value in order to make the
references function with patchwork.
On 2020-02-12 14:34:28, Dale B Stimson wrote:
> This patch series provides infrastructure to al
From: Chris Wilson
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson
Reviewed-by: Dale B Stimson
---
tests/i
d for future use?
The 2020-01-27 patches define function gem_engine_mmio_base() with its first
parameter as "fd". The new patches replace the first parameter with the
mmio_base object handle.
Chris Wilson (1):
i915/gem_ctx_isolation: Check engine relative registers
Dale B Stimson (2)
Signed-off-by: Dale B Stimson
---
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c | 346 +++
lib/i915/gem_mmio_base.h | 19 +++
lib/igt.h| 1 +
lib/meson.build | 1 +
5 files changed, 369 insertions(+)
create mode
Modify previous i915/gem_ctx_isolation "Check engine relative registers"
for modified mmio_base infrastructure.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 87 +++---
1 file changed, 48 insertions(+), 39 deletions(-)
diff --git a/
Modify previous i915/gem_ctx_isolation "Check engine relative registers"
for modified mmio_base infrastructure.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 87 +++---
1 file changed, 48 insertions(+), 39 deletions(-)
diff --git a/
From: Chris Wilson
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson
Reviewed-by: Dale B Stimson
---
tests/i
d for future use?
The 2020-01-27 patches define function gem_engine_mmio_base() with its first
parameter as "fd". The new patches replace the first parameter with the
mmio_base object handle.
Chris Wilson (1):
i915/gem_ctx_isolation: Check engine relative registers
Dale B Stimson (2)
Signed-off-by: Dale B Stimson
---
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c | 346 +++
lib/i915/gem_mmio_base.h | 19 +++
lib/igt.h| 1 +
lib/meson.build | 1 +
5 files changed, 369 insertions(+)
create mode
Modify previous i915/gem_ctx_isolation "Check engine relative registers"
for modified mmio_base infrastructure.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 87 +++---
1 file changed, 48 insertions(+), 39 deletions(-)
diff --git a/
From: Chris Wilson
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_isolation.c | 164 ++
Signed-off-by: Dale B Stimson
---
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c | 346 +++
lib/i915/gem_mmio_base.h | 19 +++
lib/igt.h| 1 +
lib/meson.build | 1 +
5 files changed, 369 insertions(+)
create mode
d for future use?
The 2020-01-27 patches define function gem_engine_mmio_base() with its first
parameter as "fd". The new patches replace the first parameter with the
mmio_base object handle.
Chris Wilson (1):
i915/gem_ctx_isolation: Check engine relative registers
Dale B Stimson (2)
Signed-off-by: Ramalingam C .
X-Original-Author: Ramalingam C
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
i
gem_context_clone_with_engines so that all contexts share
the same engine mapping.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index
1 was originally posted by Ramalingam C .
Since then, slight modifications have been done to it due to
upstream changes. Patch 1 is being kept separate from patch 2 in
order to assure proper attribution to the author.
Dale B Stimson (1):
i915/gem_ctx_isolation: gem_engine_topology, part 2
.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index c45617456..1b66fec11 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests
.
Since then, slight modifications have been done to it due to
upstream changes. Patch 1 is being kept separate from patch 2 in
order to assure proper attribution to the author.
Dale B Stimson (1):
i915/gem_ctx_isolation: use the gem_engine_topology library, part 2
Ramalingam C (1):
i915
Signed-off-by: Ramalingam C .
X-Original-Author: Ramalingam C
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
i
On 2020-01-23 15:59:33, Tvrtko Ursulin wrote:
> gem_context_clone_with_engines was agreed upon in principle some time ago
> but never implemented. I have now posted this as
> https://patchwork.freedesktop.org/series/72464/ and plan to merge it once it
> passes CI.
>
> Dale, Arjun, Krishnaiah and S
.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 41 ++
1 file changed, 32 insertions(+), 9 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 25113b054..31a20ed3a 100644
--- a/tests/i915
->class available where it is needed.
This commit is being kept separate from "part 2" in order to assure
proper attribution to the author. The code associated with this
commit was written by Ramalingam C .
Since then, slight modifications have been done due to upstream
changes.
Si
posted by Ramalingam C .
Since then, slight modifications have been done to it due to
upstream changes. Patch 1 is being kept separate from patch 2 in
order to assure proper attribution to the author.
Dale B Stimson (1):
DBS: tests/i915/gem_ctx_isolation: use the gem_engine_topology
library
:49, Chris Wilson wrote:
> Quoting Dale B Stimson (2019-03-05 01:03:08)
> > @@ -132,30 +136,49 @@ static const struct named_register {
> > { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
> > { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
> >
>
not met in function gem_require_engine, file
../lib/igt_gt.h:114:
Test requirement: gem_has_engine(gem_fd, class, instance)
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 47 +-
1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/
{ "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
{ "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
- { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .
Reviewed-By: Dale B Stimson
On Fri, Mar 01, 2019 at 08:19:19AM +, Chris Wilson wrote:
> Verify that our list of nonpriv registers exist and are writable.
>
> v2: TD_CTL has a write_mask of 0x instead of being a masked
> register.
>
> Signed-off-by: Chris Wilson
&g
On Sat, Feb 23, 2019 at 09:45:10AM +, Chris Wilson wrote:
> Verify that our list of nonpriv registers exist and are writable.
>
> Signed-off-by: Chris Wilson
> Cc: Dale B Stimson
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> ---
> tests/i915/g
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