Reviewed-by: Caz Yokoyama
Better to be safe.
On Thu, Sep 15, 2022 at 1:40 PM Lucas De Marchi
wrote:
> DSMBASE register is defined so BDSM bitfield contains the bits 63 to 20
> of the base address of stolen. For the supported platforms bits 0-19 are
> zero but that may not be true
> MTL has a fixed rawclk of 38400Mhz. Register does not need to be
> + * MTL always uses a 38.4 MHz rawclk. The bspec tells us
Mismatch between commit message and comment. Probably
38400Mhz -> 38400kHz
-caz
On Mon, Aug 1, 2022 at 8:29 PM Matt Roper wrote:
> On Wed, Jul 27, 2022 at 0
em SS registers.
>
> Bspec: 49324, 64636
>
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 49 +++--
> drivers/gpu/drm/
On Tue, Mar 22, 2022 at 2:45 PM José Roberto de Souza
wrote:
> skl_compute_ddb() will for a modeset in all pipes when MBUS joining
> changes between states, so all pipes will be disabled, have all
> MBUS related registers updated and then each pipe enabled.
>
I am not clear what you want to say h
On Fri, 2020-11-20 at 12:18 -0800, Lucas De Marchi wrote:
> On Tue, Nov 17, 2020 at 10:50:24AM -0800, Aditya Swarup wrote:
> > From: Caz Yokoyama
> >
> > The crwebview indicates on ADL-S that some of our MCHBAR
> > registers have moved from their traditional 0x50XX o
Matt,
This patch used to have version information such "v7: Add missing pipe
mask". Why they are removed? For power on?
Otherwise
Acked-by: Caz Yokoyama
-caz
On Fri, 2020-05-01 at 10:07 -0700, Matt Roper wrote:
> Introduce the basic platform definition, macros, and PCI IDs.
>
Matt Roper
Signed-off-by: Caz Yokoyama
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 20
1 file changed, 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b9b3f78f1324..f9425e5ed7ea 100644
--- a/drivers/gpu/drm/i915/gt/i
This reverts commit 36a6b5d964d995b536b1925ec42052ee40ba92c4.
The commit takes care Wa_1604544889 which was fixed on a0 stepping based on
a0 replan. So no SW workaround is required on any stepping now.
Signed-off-by: Caz Yokoyama
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 20
On Thu, 2020-02-13 at 14:37 -0800, Matt Roper wrote:
> On Tue, Feb 11, 2020 at 10:11:42AM -0800, Caz Yokoyama wrote:
> > From: "Yokoyama, Caz"
> >
> > MAD_INTER_CHANNEL_0_0_0_MCHBAR:
> > code nameoffset DRAM_DDR
From: "Yokoyama, Caz"
MAD_INTER_CHANNEL_0_0_0_MCHBAR:
code nameoffset DRAM_DDR_TYPE
SKL 0x5000 1:0 DDR4/DDR3/LPDDR3
TGL 0x6048/0x6248/0xd800 2:0 DDR4/DDR3/LPDDR3/LPDDR4
ICL 0x5000/0x6048/0x48
Reviewed-by: Caz Yokoyama
On Fri, 2019-04-05 at 12:38 +0100, Tvrtko Ursulin wrote:
> i915_vma_instance
___
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Reviewed-by: Yokoyama, Caz
-caz
On Thu, 2019-03-21 at 18:42 +, Chris Wilson wrote:
> Quoting Chris Wilson (2019-03-21 18:38:53)
> > Quoting Caz Yokoyama (2019-03-21 18:41:10)
> > > inline
> > > -caz
> > > On Thu, 2019-03-21 at 07:37 +, Chris Wilson w
inline
-caz
On Thu, 2019-03-21 at 07:37 +, Chris Wilson wrote:
> 32 is too many for the likes of kbl, and in order to insert that many
Not only kbl. ring_size is 25 on my cfl.
> requests into the ring requires us to declare the first few hung --
The hung is not caused by 32. It is caused by ac
-by: Caz Yokoyama
Cc: Chris Wilson
---
tests/i915/i915_pm_rpm.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index be296f52..9a91ca0a 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -1338,12
The part of i915_drop_caches_set() is
Reviewed-by: Yokoyama, Caz
While I don't know whether we don't really need wakeref, calling
intel_runtime_pm_get() makes GPU active state from suspended state for
example. It makes i915_pm_rpm@gem-execbuf-stress-extra-wait test
difficult to make it faster. Th
Reviewed-by: Caz Yokoyama
Correction of my test report: The patched test runs less than 7 sec on
my nuc. 10 times faster.
-caz
On Wed, 2019-02-27 at 16:29 +, Chris Wilson wrote:
> As we already have the previous portion of the mmap mlocked, we only
> need to mlock() the fresh porti
ilable memory.
>
> v2: Fixup the uint64_t pointer arithmetric and only use a single mmap
> to
> avoid subsequent mlock fail (for reasons unknown, but bet on mm/).
>
> Signed-off-by: Chris Wilson
> Cc: Caz Yokoyama
> ---
> lib/igt_aux.h | 2 +-
Reviewed-by: Caz Yokoyama
-caz
On Mon, 2019-02-25 at 18:29 +, Chris Wilson wrote:
> Quoting Caz Yokoyama (2019-02-25 18:28:34)
> > Chris,
> > By your patch, measure_qlen() reports how many gem_execbuf() can be
> > executed(queue length) within timeout of the slowes
waiting for those to complete at
> the
> end of our subtest timeslice.
>
> Signed-off-by: Chris Wilson
> Cc: Caz Yokoyama
> ---
> tests/i915/gem_ctx_switch.c | 39 +
>
> 1 file changed, 31 insertions(+), 8 deletions(-)
>
>
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