On Tue, 2019-07-30 at 11:04 -0700, Lucas De Marchi wrote:
> From: Tomasz Lis
>
> The MOCS table is published as part of bspec, and versioned. Entries
> are supposed to never be modified, but new ones can be added. Adding
> entries increases table version. The patch includes version 1
> entries.
>
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> The final save operation into pll_state of the calculations done will
> be different for DKL PHY. Prepare for that by reindenting code so
> it's
> easier to check for correctness. This one has no change in behavior.
>
Reviewed-by: Matt At
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni
>
> These are the registers needed to program Dekel PHY. Some register
> definitions reuse the MG PHY definitions. Add a comment on those so
> we
> don't need to duplicate the functions for programming them.
>
Rev
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa
>
> Add Support to load DMC v2.02 on TGL.
>
Reviewed-by: Matt Atwood
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_csr.c | 7 +++
> 1 file changed, 7 i
On Thu, 2019-07-18 at 11:17 +0530, Anshuman Gupta wrote:
> On 2019-07-12 at 18:09:39 -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza
> >
> > Tiger Lask has a new register offset for DC5 and DC6 residency
> > counters.
nit: Tiger Lake
> >
> > Signed-off-by: José Roberto de Souza
>
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
> it's at offset 24. Similarly TC port (5/6) clk off bits are at
> offset 22/23. Extend the macros to cover the additional ports.
>
Reviewed-by: Ma
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> According to the spec when initializing the display in TGL we should
> not
> set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-
> use the
> power well hooks from ICL so only set this register on gen < 12.
>
> v2: Generali
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> Bit definitions for port-select got changed for TRANS_CLK_SEL &
> TRANS_DDI_FUNC_CTL registers in TGL.
>
> v2 (Lucas):
> - Nuke TRANS_DDI_PORT_NONE since it's 0: we are already clearing
> {TGL_,}TRANS_DDI_PO
On Tue, 2019-06-04 at 23:16 +0300, Ville Syrjälä wrote:
> On Tue, Jun 04, 2019 at 12:44:48PM -0700, Manasi Navare wrote:
> > On Tue, Jun 04, 2019 at 03:51:58PM +0300, Ville Syrjälä wrote:
> > > On Mon, Jun 03, 2019 at 02:49:40PM -0700,
> > > matthew.s.atw...@intel.com wrote:
> > > > From: Matt Atw
On Thu, 2018-11-29 at 15:37 -0800, Rodrigo Vivi wrote:
> On Thu, Nov 29, 2018 at 10:54:50PM +0000, Atwood, Matthew S wrote:
> > On Thu, 2018-11-29 at 14:00 -0800, Manasi Navare wrote:
> > > From: Matt Atwood
> > >
> > > Accordi
On Thu, 2018-11-29 at 14:00 -0800, Manasi Navare wrote:
> From: Matt Atwood
>
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 0
On Thu, 2018-11-15 at 11:48 -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> The calibration RCOMP value in PORT_TX_DW6 in stored in dev_priv
> during
> driver init. Use this value instead of reading the register again as
> the
> power well for PORTA RCOMP register may not be ena
On Thu, 2018-07-19 at 14:07 -0700, Rodrigo Vivi wrote:
> On Thu, Jul 19, 2018 at 01:35:49PM -0700, matthew.s.atw...@intel.com
> wrote:
> > From: Matt Atwood
> >
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> > DPCD
> > 0220
ill uprev by EOD
From: Navare, Manasi D
Sent: Monday, June 25, 2018 5:39 PM
To: Atwood, Matthew S
Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo; ble...@chromium.org;
Zanoni, Paulo R
Subject: Re: [Intel-gfx] [PATCH] drm/dp: implement
On Thu, 2018-05-17 at 12:50 +0300, Jani Nikula wrote:
> On Wed, 16 May 2018, Dhinakaran Pandiyan om> wrote:
> > On Wed, 2018-05-16 at 09:33 -0700, matthew.s.atw...@intel.com
> > wrote:
> > > From: Matt Atwood
> > >
> > > According to DP spec (2.9.3.1 of DP 1.4) if
> > > EXTENDED_RECEIVER_CAPABIL
On Wed, 2018-05-09 at 08:09 -0700, Matt Atwood wrote:
> On Wed, 2018-05-09 at 05:21 -0700, Rodrigo Vivi wrote:
> > On Wed, May 09, 2018 at 10:13:21AM +0300, Jani Nikula wrote:
> > > We've opted to use the maximum link rate and lane count for eDP
> > > panels,
> > > because typically the maximum sup
On Wed, 2018-05-09 at 05:21 -0700, Rodrigo Vivi wrote:
> On Wed, May 09, 2018 at 10:13:21AM +0300, Jani Nikula wrote:
> > We've opted to use the maximum link rate and lane count for eDP
> > panels,
> > because typically the maximum supported configuration reported by
> > the
> > panel has matched t
On Fri, 2018-03-09 at 14:05 +0200, Jani Nikula wrote:
> On Thu, 08 Mar 2018, matthew.s.atw...@intel.com wrote:
> >
> > From: Matt Atwood
> >
> > Previously it was assumed that eDP panels would advertise the
> > lowest link
> > rate required for their singular mode to function. With the
> > intro
On Thu, 2018-03-08 at 09:22 +0200, Jani Nikula wrote:
> On Wed, 07 Mar 2018, matthew.s.atw...@intel.com wrote:
> >
> > From: Matt Atwood
> >
> > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme
> > from 8
> > bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
> >
ithout DMC.
From: Deak, Imre
Sent: Wednesday, June 14, 2017 1:17 PM
To: Rodrigo Vivi
Cc: Atwood, Matthew S; intel-gfx@lists.freedesktop.org; marc...@google.com;
Matt Atwood
Subject: Re: [Intel-gfx] [PATCH] drm/i915: decouple runtime PM enablement from
DMC presence
On Wed, Jun 14, 2017 at
From: Rodrigo Vivi [rodrigo.v...@gmail.com]
Sent: Wednesday, June 14, 2017 1:02 PM
To: Deak, Imre
Cc: Atwood, Matthew S; intel-gfx@lists.freedesktop.org; marc...@google.com;
Matt Atwood
Subject: Re: [Intel-gfx] [PATCH] drm/i915: decouple runtime PM enablement from
DMC presence
On W
t DMC loaded we want to keep runtime PM disabled" - Why?
From: Deak, Imre
Sent: Wednesday, June 14, 2017 10:33 AM
To: Atwood, Matthew S
Cc: intel-gfx@lists.freedesktop.org; marc...@google.com; Matt Atwood
Subject: Re: [Intel-gfx] [PATCH] drm/i915: decoup
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