On Fri, 2017-06-30 at 17:29 +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 6/30/2017 5:04 PM, Ander Conselvan De Oliveira wrote:
> > On Fri, 2017-06-30 at 11:20 +0530, Sharma, Shashank wrote:
> > > Regards
> > >
> > > Shash
On Fri, 2017-06-30 at 17:47 +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 6/30/2017 5:37 PM, Ander Conselvan De Oliveira wrote:
> > On Wed, 2017-06-21 at 16:04 +0530, Shashank Sharma wrote:
> > > This patch sets the is_hdmi2_src identifi
d are separate prep patches. But anyway, you can
use
Reviewed-by: Ander Conselvan de Oliveira
on those if you want.
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm
On Fri, 2017-06-30 at 11:20 +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 6/27/2017 5:46 PM, Ander Conselvan De Oliveira wrote:
> > On Wed, 2017-06-21 at 16:04 +0530, Shashank Sharma wrote:
> > > To get a YCBCR420 output from intel platforms,
On Fri, 2017-06-30 at 11:33 +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 6/29/2017 5:38 PM, Ander Conselvan De Oliveira wrote:
> > On Wed, 2017-06-21 at 16:04 +0530, Shashank Sharma wrote:
> > > To support ycbcr HDMI output, we need a pipe CSC
ase
> V3: Rebase
> V4: Rebase
>
> Cc: Ville Syrjala
> Cc: Daniel Vetter
> Cc: Ander Conselvan De Oliveira
> Signed-off-by: Shashank Sharma
> ---
> drivers/gpu/drm/i915/intel_color.c | 47
> +++-
> drivers/gpu/drm/i915/intel_dis
ister for ycbcr420 output.
> - Adds a new scaler user "HDMI output" to plug-into existing
> scaler framework. This output type is identified using bit
> 30 of the scaler users bitmap.
>
> V2: rebase
> V3: rebase
> V4: rebase
>
> Cc: Ville Syrjala
> Cc: And
On Wed, 2017-06-21 at 21:19 +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 6/20/2017 7:50 PM, Ander Conselvan De Oliveira wrote:
> > On Mon, 2017-06-19 at 21:38 +0530, Shashank Sharma wrote:
> > > This patch checks encoder level support for HDMI
commits the hdmi output type into crtc state,
> for further staging in driver.
>
> V2: Split the patch into two, kept helper functions in DRM layer.
> V3: Changed the compute_config function based on new DRM API.
> V4: Rebase
>
> Cc: Ville Syrjala
> Cc: Daniel Vette
On Wed, 2017-06-14 at 14:16 -0700, Matt Roper wrote:
> On Wed, Jun 14, 2017 at 02:47:06PM +0300, Ander Conselvan De Oliveira wrote:
> > On Tue, 2017-06-13 at 12:06 -0700, Rodrigo Vivi wrote:
> > > On Tue, Jun 13, 2017 at 11:07 AM, Matt Roper
> > > wrote:
> >
On Thu, 2017-06-15 at 09:44 +0530, Mahesh Kumar wrote:
> Hi Ander,
>
>
> On Wednesday 14 June 2017 05:17 PM, Ander Conselvan De Oliveira wrote:
> > On Tue, 2017-06-13 at 12:06 -0700, Rodrigo Vivi wrote:
> > > On Tue, Jun 13, 2017 at 11:07 AM, Matt Roper
> >
On Tue, 2017-06-13 at 12:06 -0700, Rodrigo Vivi wrote:
> On Tue, Jun 13, 2017 at 11:07 AM, Matt Roper
> wrote:
> > On Tue, Jun 13, 2017 at 10:52:30AM -0700, Rodrigo Vivi wrote:
> > > This reverts commit bb9d85f6e9de8fef5236c076530eab67a2f2431b.
> > >
> > > New ddb allocation algorithm is a show
On Fri, 2017-06-09 at 08:43 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/glk: Remove the alpha_support flag
> URL : https://patchwork.freedesktop.org/series/25471/
> State : failure
>
> == Summary ==
>
> Series 25471v1 drm/i915/glk: Remove the alpha_support flag
> https:
Geminilake is now included in CI, making it part of the pre-merge
criteria. The support should be in good enough shape, so let's remove
the alpha_support flag.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --
On Fri, 2017-05-26 at 16:23 -0700, Rodrigo Vivi wrote:
> According to spec this WA is needed for every gen9.
Actually GLK has a gen10 display, so the gen9 workarounds don't apply.
Ander
>
> Cc:Arthur Runyan
> Cc: Ander Conselvan de Oliveira
> Signed-off-by: Rodrigo Vivi
On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> From: Paulo Zanoni
>
> They're slightly different than the gen 9 calculations.
I missed this at first, but GLK should follow the gen10 watermark programming as
it has a gen10 display.
>
> TODO: before upstraming this, check if the spec i
On Wed, 2017-05-24 at 13:57 +0530, Mahesh Kumar wrote:
> Hi,
>
>
> On Monday 08 May 2017 02:20 PM, Ander Conselvan de Oliveira wrote:
> > In Geminilake, a FIFO underrun happens the first time a pipe scaler is
> > enabled after boot/resume from suspend. Disabling DPF
On Thu, 2017-05-18 at 18:06 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/huc: Update GLK HuC version
> URL : https://patchwork.freedesktop.org/series/24641/
> State : success
Pushed, thanks for the patch.
Ander
>
> == Summary ==
>
> Series 24641v1 drm/i915/huc: Update
On Thu, 2017-05-18 at 10:47 -0700, Anusha Srivatsa wrote:
> Update version of HuC from 01.07.1748 to the
> version 02.00.1748
>
> Cc: Ander Conselvan
> Cc: John Spotswood
> Signed-off-by: Anusha Srivatsa
Reviewed-by: Ander Conselvan de Oliveira
> ---
> drivers/gpu/
On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> Let's inherit workarounds from previous platforms that
> according to wa_database and BSpec are still valid for
> Cannonlake.
>
> v2: Add missed workarounds.
> v3: Rebase
>
> Cc: Mika Kuoppala
> Signed-off-by: Rodrigo Vivi
> ---
> driver
alloc_size);
> + return-EINVAL;
> + }
The comments I made earlier [1] are still valid. With those fixed and a
changelog in the commit message,
Reviewed-by: Ander Conselvan de Oliveira
[1] https://lists.freedesktop.org/archives/intel-gfx/2017-April/125764.
In Geminilake, a FIFO underrun happens the first time a pipe scaler is
enabled after boot/resume from suspend. Disabling DPF clock gating in
the respective CLKGATE_DIS_PSL register prior to enabling the scaler
works around the issue.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu
u32 temp;
> +
> + temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> + id = temp >> (port * 2);
Maybe use DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT which was defined in the previous
patch?
Also, might make sense to squash this with the next patch, but
is getting updated to do DDI -> PLL mapping
> and clock on in 2 separated reg writes. (Paulo)
> Also update bits definitions to use space
> (1 << 1) instead of (1<<1). (Paulo)
>
> Cc: Paulo Zanoni
> Cc: Art Runyan
> Cc: Clint Taylor
> Cc: V
> > (1 << 1) instead of (1<<1). (Paulo)
> >
> > Cc: Paulo Zanoni
> > Cc: Art Runyan
> > Cc: Clint Taylor
> > Cc: Ville Syrjälä
> > Cc: Kahola, Mika
> > Cc: Ander Conselvan De Oliveira > m>
> > Signed-off-by
On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> From: James Irwin
>
> Issue: VIZ-4525
>
> Reviewed-by: Damien Lespiau
> Signed-off-by: James Irwin
> Signed-off-by: Damien Lespiau
Reviewed-by: Ander Conselvan de Oliveira
> ---
> drivers/gpu/drm/i
> +static const struct intel_device_info intel_cannonlake_info = {
> + BDW_FEATURES,
> + .is_alpha_support = 1,
> + .platform = INTEL_CANNONLAKE,
> + .gen = 10,
> + .ddb_size = 896,
> +};
> +
I think it makes sense to squash patch 17 with this one.
On Fri, 2017-04-28 at 12:44 +, Chauhan, Madhav wrote:
> > -Original Message-
> > From: Ander Conselvan De Oliveira [mailto:conselv...@gmail.com]
> > Sent: Friday, April 28, 2017 2:28 PM
> > To: Chauhan, Madhav ; intel-
> > g...@lists.freedesktop.org
&
> >
> > [drm:glk_dsi_device_ready [i915]] *ERROR* ULPS is still active
> >
> > Fixes: 4644848369c0 ("drm/i915/glk: Add MIPIIO Enable/disable sequence")
> > Cc: Deepak M
> > Cc: Madhav Chauhan
> > Cc: Jani Nikula
> > Cc: Daniel Vetter
>
esktop.org
Cc:
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dsi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3ffe8b1..fc0ef49 100644
--- a/drivers/gpu/drm/i915/i
On Mon, 2017-04-24 at 11:22 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/glk: Don't allow 12 bpc when htotal is too big
> URL : https://patchwork.freedesktop.org/series/23451/
> State : success
Pushed, thanks for reviewing.
Ander
>
> == Summary ==
>
> Series 23451v1 d
On Mon, 2017-04-24 at 16:49 +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 4/24/2017 4:17 PM, Ander Conselvan de Oliveira wrote:
> > Display workaround #1139 for Geminilake instructs us to restrict HDMI
> > to 8 bpc when htotal is greater than 5460.
On Tue, 2017-04-25 at 05:29 +, Vivi, Rodrigo wrote:
> > On Apr 24, 2017, at 10:57 AM, Ville Syrjälä
> > wrote:
> >
> > > On Thu, Apr 06, 2017 at 12:15:54PM -0700, Rodrigo Vivi wrote:
> > > Cannonlake has same color setup as Geminilake.
> > > Legacy color load luts doesn't work anymore on Can
On Mon, 2017-04-24 at 13:47 +0300, Ander Conselvan de Oliveira wrote:
> Display workaround #1139 for Geminilake instructs us to restrict HDMI
> to 8 bpc when htotal is greater than 5460. Otherwise, the pipe is unable
> to generate a proper signal and is left in a state where corruption
=100440
Cc: Shashank Sharma
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_hdmi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 6efc3cb..52f0b2d 100644
--- a/drivers/gpu/drm/i915
ed by limited range rgb, force all
tests to use full range. It is still possible for tests to override this
if necessary.
v2: Add more details to the commit message.
v3: Force all tests to use full range.
Cc: Ville Syrjälä
Signed-off-by: Ander Conselvan de Oliveira
---
lib/igt_kms.c | 7 +
On Tue, 2017-02-28 at 17:01 +0530, Mahesh Kumar wrote:
> DDB minimum requirement may also exceed the allocated DDB for CRTC.
> Instead of directly deducting from alloc_size, check against
> total_min_ddb requirement. if exceeding fail the flip.
Instead of doing a low level description of the code
ommit message.
Signed-off-by: Ander Conselvan de Oliveira
---
tests/kms_cursor_crc.c | 8
1 file changed, 8 insertions(+)
diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c
index 206f852..1208d90 100644
--- a/tests/kms_cursor_crc.c
+++ b/tests/kms_cursor_crc.c
@@ -372,6 +3
ot;")
Cc: Chris Wilson
Signed-off-by: Ander Conselvan de Oliveira
---
lib/igt_debugfs.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index d64694c..fb6d521 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -2
On Thu, 2017-03-30 at 20:43 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/GuC/GLK: Load GuC on GLK
> URL : https://patchwork.freedesktop.org/series/22237/
> State : success
Pushed to dinq. Thanks for the patches and reviews!
Ander
>
> == Summa
planes support higher bit depths, since the failures
happens with specific color values, but that's speculation.
Signed-off-by: Ander Conselvan de Oliveira
---
tests/kms_cursor_crc.c | 8
1 file changed, 8 insertions(+)
diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c
it is here
to prove the point of the previous patch.
Signed-off-by: Ander Conselvan de Oliveira
---
tests/Makefile.sources | 1 +
tests/kms_cursor_limited.c | 175 +
2 files changed, 176 insertions(+)
create mode 100644 tests
On Tue, 2017-04-04 at 10:27 +, Chauhan, Madhav wrote:
> > -Original Message-
> > From: Nikula, Jani
> > Sent: Tuesday, April 4, 2017 3:48 PM
> > To: Ander Conselvan De Oliveira ; intel-
> > g...@lists.freedesktop.org
> > Cc: Chauhan, Madhav ; Ville
On Tue, 2017-04-04 at 11:40 +0300, Jani Nikula wrote:
> On Tue, 04 Apr 2017, Ander Conselvan De Oliveira wrote:
> > On Tue, 2017-04-04 at 11:15 +0300, Jani Nikula wrote:
> > > From: Madhav Chauhan
> > >
> > > As per BSPEC, valid cdclk values for glk are 79.2,
limit
> v4 by Jani:
> - drop superfluous whitespace change
> - rewrite code comments to clarify
>
> Cc: Ander Conselvan de Oliveira
> Cc: Ville Syrjälä
> Signed-off-by: Madhav Chauhan
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_cdclk
On Mon, 2017-03-27 at 12:23 +0100, Chris Wilson wrote:
> On Mon, Mar 27, 2017 at 02:08:28PM +0300, Ander Conselvan de Oliveira wrote:
> > Currently, the main thread needs to wakeup to run the signal handler
> > that ends a spin batch. When testing whether a function call succesfull
: Get rid of mutexes. (Chris)
Cc: Chris Wilson
Signed-off-by: Ander Conselvan de Oliveira
---
lib/igt_dummyload.c | 45 ++---
lib/igt_dummyload.h | 1 -
2 files changed, 6 insertions(+), 40 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib
: Chris Wilson
Signed-off-by: Ander Conselvan de Oliveira
---
lib/igt_dummyload.c | 55 +
lib/igt_dummyload.h | 3 ++-
2 files changed, 19 insertions(+), 39 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 019c1fb
On Thu, 2016-12-01 at 11:23 +, Chris Wilson wrote:
> On Thu, Dec 01, 2016 at 12:58:46PM +0200, Abdiel Janulgue wrote:
> > Signed-off-by: Abdiel Janulgue
How is the bug that this commit fixes triggered? Reverting this change seems to
fix [1] which, if I understand correctly, is caused by the a
have
intel_legacy_cursor_update() call into watermark code to ask if it can proceed
or not, instead of making assumptions of what can cause watermarks to change.
But since the duplicated assumptions were there before, this fix doesn't make
the overall situation any worse.
Acked-by: Ander Co
On Thu, 2017-03-02 at 16:58 +0200, Ville Syrjälä wrote:
> On Sat, Feb 25, 2017 at 04:31:04PM +0100, Maarten Lankhorst wrote:
> > Op 24-02-17 om 14:11 schreef Ville Syrjälä:
> > > On Mon, Feb 20, 2017 at 03:30:58PM +0100, Maarten Lankhorst wrote:
> > > > Op 20-02-17 om 14:38 schreef Ville Syrjälä:
>
to kernel pooled EU configure.").
v2: Improve commit message. (Mika, Roy)
Cc: Arun Siluvery
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Cc: Yang Rong
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_device_info.c | 9 +
1 file changed, 5 insertions(+), 4 deletions
On Tue, 2017-03-14 at 13:01 -0700, Manasi Navare wrote:
> From: "Navare, Manasi D"
>
> Display stream compression is supported on DP 1.4 DP
> devices. This patch adds the corersponding DPCD
> register definitions for DSC.
>
> v3:
> * Add some SHIFTS and MASKS for uniformity (Jani Nikula)
> v2:
>
On Thu, 2017-03-16 at 15:10 +0200, Jani Nikula wrote:
> On Thu, 16 Mar 2017, "Chauhan, Madhav" wrote:
> > > -Original Message-
> > > From: Nikula, Jani
> > > Sent: Thursday, February 16, 2017 9:03 PM
> > > To: Chauhan, Madhav ; intel-
> > > g...@lists.freedesktop.org
> > > Cc: Conselvan De
ha Srivatsa
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: intel-gfx@lists.freedesktop.org
Cc:
Signed-off-by: Ander Conselvan de Oliveira
Acked-by: Jani Nikula
Link:
http://patchwork.freedesktop.org/patch/msgid/20170306085651.14008-1-ander.conselvan.de.olive...@intel.com
(cherry pic
On Fri, 2017-03-10 at 12:27 +0200, Ander Conselvan De Oliveira wrote:
> On Fri, 2017-03-10 at 12:18 +0200, Ander Conselvan de Oliveira wrote:
> > Some of the kms_cursor_crc subtests where failing on Geminilake. The
> > root cause was an error on programming the pre-CSC gamma tables
On Fri, 2017-03-10 at 13:18 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/glk: Improve rounding caused by pre-CSC gamma tables
> URL : https://patchwork.freedesktop.org/series/21049/
> State : success
Pushed. Thanks for reviewing.
Ander
>
> == Summary ==
>
> Series 210
nder
> - Pass the scrambling state variables as bool input to the sink_scrambling
>function and let the disable call be unconditional.
> - Fix alignments in function calls and debug messages.
> - Add kernel doc for function intel_hdmi_handle_sink_scrambling
>
> V10: Rebase
&g
On Thu, 2017-03-09 at 17:17 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Remove intel_ prefix from encoder variables in intel_ddi.c
> URL : https://patchwork.freedesktop.org/series/20992/
> State : success
Pushed to drm-intel-next-queued. Thanks for the patch.
Ander
>
On Fri, 2017-03-10 at 12:18 +0200, Ander Conselvan de Oliveira wrote:
> Some of the kms_cursor_crc subtests where failing on Geminilake. The
> root cause was an error on programming the pre-CSC gamma tables, which
> led to small rounding errors that, although not sufficient to change th
: Ander Conselvan de Oliveira
---
tests/kms_cursor_crc.c | 42 ++
1 file changed, 38 insertions(+), 4 deletions(-)
diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c
index 4851e18..0b232bf 100644
--- a/tests/kms_cursor_crc.c
+++ b/tests
e CRC mismatches.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_color.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index b9e5266d..306c6b0 100644
--- a/drivers/gpu/drm
The summary should say what the clean up is about. For example:
drm/i915: Remove intel_ prefix from encoder variables in intel_ddi.c
With that fixed,
Reviewed-by: Ander Conselvan de Oliveira
On Thu, 2017-03-09 at 16:28 +0530, Shashank Sharma wrote:
> In I915 driver, there are many pla
On Wed, 2017-03-08 at 19:07 +0530, Shashank Sharma wrote:
> Geminilake platform sports a native HDMI 2.0 controller, and is
> capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
> mendates scrambling for these higher clocks, for reduced RF footprint.
>
> This patch checks if the monitor
On Fri, 2017-03-03 at 21:58 +0530, Shashank Sharma wrote:
> Geminilake platform sports a native HDMI 2.0 controller, and is
> capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
> mendates scrambling for these higher clocks, for reduced RF footprint.
>
> This patch checks if the monitor sup
On Wed, 2017-02-22 at 21:22 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/: DMC 1.04 for Geminilake
> URL : https://patchwork.freedesktop.org/series/20091/
> State : warning
>
> == Summary ==
>
> Series 20091v1 drm/i915/: DMC 1.04 for Geminilake
> https://patchwork.freede
usha Srivatsa
Reviewed-by: Ander Conselvan de Oliveira
> ---
> drivers/gpu/drm/i915/intel_csr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index 14659c7..34aa9fa 10
On Mon, 2017-03-06 at 10:24 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/glk: Remove MODULE_FIRMWARE() tag from Geminilake's DMC
> URL : https://patchwork.freedesktop.org/series/20744/
> State : success
Pushed to drm-intel-next-queued.
Thanks,
Ander
>
> == Summary ==
>
ha Srivatsa
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: intel-gfx@lists.freedesktop.org
Cc:
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_csr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1
that uses this only cares
> > about the 3x6 configuration. See Beignet's commit 6901899ec90a
> > ("Runtime: set the sub slice according to kernel pooled EU configure.").
> >
> > Cc: Arun Siluvery
> > Cc: Mika Kuoppala
> > Cc: Tvrtko Ursulin
&
On Fri, 2017-03-03 at 17:33 +0530, Sharma, Shashank wrote:
> Thanks for the review Ander. My comments inline.
>
> Shashank
>
> On 3/3/2017 3:22 PM, Ander Conselvan De Oliveira wrote:
> > On Fri, 2017-03-03 at 11:59 +0530, Shashank Sharma wrote:
> > > Geminilake pla
On Tue, 2017-02-28 at 18:57 -0800, Dhinakaran Pandiyan wrote:
> According to BSpec, "The CD clock frequency must be at least twice the
> frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> default. BXT and GLK both have cdclk frequencies that are less han 192 MHz,
> so apply the ch
On Tue, 2017-02-28 at 18:57 -0800, Dhinakaran Pandiyan wrote:
> Implement GLK cdclk restriction for DP audio, similar to what's implemented
> for BDW and other GEN9 platforms. The cdclk restriction has been
> refactored out of max. pixel clock computation as the 1:1 relationship
> between pixel clo
On Mon, 2017-02-20 at 17:00 -0300, Paulo Zanoni wrote:
> There's a lot of duplicated platform-independent logic in the current
> modeset_calc_cdclk() functions. Adding cdclk support for more
> platforms will only add more copies of this code.
>
> To solve this problem, in this patch we create a ne
On Thu, 2017-03-02 at 13:48 +, Patchwork wrote:
> == Series Details ==
>
> Series: Try to fix MST regression with DDI IO power domains (rev5)
> URL : https://patchwork.freedesktop.org/series/20345/
> State : failure
>
> == Summary ==
>
> Series 20345v5 Try to fix MST regression with DDI IO
On Fri, 2017-03-03 at 11:59 +0530, Shashank Sharma wrote:
> Geminilake platform sports a native HDMI 2.0 controller, and is
> capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
> mendates scrambling for these higher clocks, for reduced RF footprint.
>
> This patch checks if the monitor sup
On Thu, 2017-03-02 at 08:25 +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 3/1/2017 8:41 PM, Ville Syrjälä wrote:
> > On Tue, Feb 28, 2017 at 02:09:09PM +0530, Shashank Sharma wrote:
> > > Geminilake platform sports a native HDMI 2.0 controller, and is
> > > capable of driving pi
On Thu, 2017-03-02 at 11:17 +, Patchwork wrote:
> == Series Details ==
>
> Series: i915/HuC: Add an extra check for platforms that do not have HUC
> URL : https://patchwork.freedesktop.org/series/20482/
> State : success
Pushed. Thanks for the patch.
Ander
>
> == Summary ==
>
> Series 2
On Wed, 2017-03-01 at 11:58 -0800, Anusha Srivatsa wrote:
> Return silently without producing much noise on platforms
> that have a HuC but the firmware is absent.
Matches what's done for GuC.
Reviewed-by: Ander Conselvan de Oliveira
> Cc: Ander Conselvan De Oliveira
>
v3: Warn for MST + PORT_E too. (Ville)
Cc: Imre Deak
Cc: Ville Syrjälä
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c| 2 ++
drivers/gpu/drm/i915/intel_dp_mst.c | 23 +++
2 files changed, 5 insertions(+), 20 d
drm_crtc in the callers.
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 62
drivers/gpu/drm/i915/intel_display.c | 8 ++---
drivers/gpu/drm/i915/intel_drv.h | 6 ++--
3 files changed, 34
Remove direct usages of intel_crtc->config from the DDI code. Functions
that didn't yet take a pipe_config as an argument were coverted to do
so.
v2: s/pipe_config/const crtc_state/ (Ville)
- take crtc from crtc_state. (Ville)
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-b
It is preferred to pass pipe_config to functions instead of accessing
crtc->config directly. Follow suit and pass pipe_config to the fdi link
train functions.
v2: Add const; s/pipe_config/crtc_state/ (Ville)
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Ville Syrjälä
---
drivers/
Using crtc->config directly is being removed in favor of passing a
pipe_config. Follow the trend and pass pipe_config to pch_enable()
functions.
v2: s/pipe_config/crtc_state/ (Ville)
- constify crtc_state. (Ville)
- take crtc from crtc_state. (Ville)
Signed-off-by: Ander Conselvan de Olive
The function intel_lpt_pch_enable() needs an intel_crtc so pass that
instead of the generic crtc type.
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff
Improve the clean ups, as requested by Ville:
- s/pipe_config/crtc_state/
- constify crtc_state
- only pass state instead of crtc and state
Ander Conselvan de Oliveira (7):
drm/i915: Pass intel_crtc to fdi_link_train() hooks
drm/i915: Pass intel_crtc to intel_lpt_pch_enable()
drm
The implementation of the fdi_link_train() hooks need an intel_crtc so
just pass that instead of the generic crtc type.
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 13
It is preferred to pass pipe_config to functions instead of accessing
crtc->config directly. Follow suit and pass pipe_config to the fdi link
train functions.
v2: Add const; s/pipe_config/crtc_state/ (Ville)
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_dr
Using crtc->config directly is being removed in favor of passing a
pipe_config. Follow the trend and pass pipe_config to pch_enable()
functions.
v2: s/pipe_config/crtc_state/ (Ville)
- constify crtc_state. (Ville)
- take crtc from crtc_state. (Ville)
Signed-off-by: Ander Conselvan de Olive
On Wed, 2017-03-01 at 16:13 +0200, Ander Conselvan de Oliveira wrote:
> Commit 62b695662a24 ("drm/i915: Only enable DDI IO power domains after
> enabling DPLL") changed how the DDI IO power domains get enabled, but
> neglected the need to enable those domains when enabling a
t all CPUs entered broadcast
exception handler
Fixes: 62b695662a24 ("drm/i915: Only enable DDI IO power domains after enabling
DPLL")
Cc: David Weinehall
Cc: Imre Deak
Cc: Ander Conselvan de Oliveira
Cc: David Weinehall
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: intel-gfx@lists.freed
Cc: Imre Deak
Cc: Ville Syrjälä
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_ddi.c| 2 ++
drivers/gpu/drm/i915/intel_dp_mst.c | 23 +++
2 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers
It is preferred to pass pipe_config to functions instead of accessing
crtc->config directly. Follow suit and pass pipe_config to the fdi link
train functions.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_ddi.c |
Remove direct usages of intel_crtc->config from the DDI code. Functions
that didn't yet take a pipe_config as an argument were coverted to do
so.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_ddi.c | 61 +++-
drivers/gpu/
The function intel_lpt_pch_enable() needs an intel_crtc so pass that
instead of the generic crtc type.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm
The implementation of the fdi_link_train() hooks need an intel_crtc so
just pass that instead of the generic crtc type.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 13
drivers/gpu/drm/i915
Hi,
Here's a v2 of the fix for the regression caused by the recent DDI IO
power domain changes. This time with moar patches and actual testing.
The new patches remove the usage of crtc->config from intel_ddi.c and
that also removes the oops with encoder->crtc being NULL.
Ander C
drm_crtc in the callers.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_ddi.c | 62
drivers/gpu/drm/i915/intel_display.c | 8 ++---
drivers/gpu/drm/i915/intel_drv.h | 6 ++--
3 files changed, 34 insertions(+), 42 deletions
Using crtc->config directly is being removed in favor of passing a
pipe_config. Follow the trend and pass pipe_config to pch_enable()
functions.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 18 ++
1 file changed, 10 insertions(+)
On Tue, 2017-02-28 at 07:53 +, Patchwork wrote:
> == Series Details ==
>
> Series: Try to fix MST regression with DDI IO power domains
> URL : https://patchwork.freedesktop.org/series/20345/
> State : failure
>
> == Summary ==
>
> Series 20345v1 Try to fix MST regression with DDI IO power
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