[Intel-gfx] [PATCH v4] drm/i915/bdw: Check for slice, subslice and EU count for BDW

in Cherryview and Gen9 sseu_device_satus functions v3: - Fix style issues v4: - Corrected comment - Reverted reordering of defines Cc: Jeff Mcgee Cc: Arun Siluvery Signed-off-by: Łukasz Daniluk --- drivers/gpu/drm/i915/i915_debugfs.c | 29 +- drivers/gpu/drm/i915/i915_dma.c

[Intel-gfx] [PATCH v3] drm/i915/bdw: Check for slice, subslice and EU count for BDW

in Cherryview and Gen9 sseu_device_satus functions v3: - Fix style issues Cc: Jeff Mcgee Cc: Arun Siluvery Signed-off-by: Łukasz Daniluk --- drivers/gpu/drm/i915/i915_debugfs.c | 29 +- drivers/gpu/drm/i915/i915_dma.c | 80 + drivers/gpu

[Intel-gfx] [PATCH v2] drm/i915/bdw: Check for slice, subslice and EU count for BDW

in Cherryview and Gen9 sseu_device_satus functions Cc: Jeff Mcgee Signed-off-by: Łukasz Daniluk --- drivers/gpu/drm/i915/i915_debugfs.c | 29 +++- drivers/gpu/drm/i915/i915_dma.c | 89 + drivers/gpu/drm/i915/i915_reg.h | 22 - 3

[Intel-gfx] [PATCH] drm/i915/bdw: Check for slice, subslice and EU count for BDW

into account. It can be read in debugfs. Introduce new register defines that contain information on slices on Broadwell. Cc: Jeff Mcgee Signed-off-by: Łukasz Daniluk --- drivers/gpu/drm/i915/i915_debugfs.c | 35 +-- drivers/gpu/drm/i915/i915_dma.c | 89