== Series Details ==
Series: Introduce set_context_latency and refactor VRR/DSB timing logic (rev3)
URL : https://patchwork.freedesktop.org/series/154810/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_17264 -> Patchwork_154810v3
On Tue, Sep 23, 2025 at 05:31:04PM +0300, Jani Nikula wrote:
> i915_irq.c no longer needs display/intel_psr_regs.h. Drop it.
>
> Signed-off-by: Jani Nikula
My compiler said it's ok. I trust it, most of the time.
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_irq.c | 1 -
> 1 fi
On Tue, Sep 23, 2025 at 04:02:44PM +0530, Nautiyal, Ankit K wrote:
>
> On 9/22/2025 4:27 PM, Ville Syrjälä wrote:
> > On Sun, Sep 21, 2025 at 10:05:35AM +0530, Ankit Nautiyal wrote:
> >> The maximum guardband value is constrained by two factors:
> >> - The actual vblank length minus set context la
The maximum guardband value is constrained by two factors:
- The actual vblank length minus set context latency (SCL)
- The hardware register field width:
- 8 bits for ICL/TGL (VRR_CTL_PIPELINE_FULL_MASK -> max 255)
- 16 bits for ADL+ (XELPD_VRR_CTL_VRR_GUARDBAND_MASK -> max 65535)
Remove the
On Mon, Sep 22, 2025 at 11:06:02PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 22, 2025 at 10:35:42PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 19, 2025 at 12:12:22AM +0300, Imre Deak wrote:
> > > Read out the branch devices' maximum overall DSC pixel throughput and
> > > line width and verify the
From: Ville Syrjälä
Move intel_cdclk_atomic_check() a bit so that we don't need an
extra intel_modeset_calc_cdclk() forward declaration.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 82 +++---
1 file changed, 40 insertions(+), 42 deletions(-)
d
