MEI GSC interrupt comes from i915. It has top half and bottom half.
Top half is called from i915 interrupt handler. It should be in
irq disabled context.
With RT kernel, by default i915 IRQ handler is in threaded IRQ. MEI GSC
top half might be in threaded IRQ context. In this case, local IRQ
shoul
As reported by Andy, kernel-doc.py is creating a __pycache__
directory at build time.
Disable creation of __pycache__ for the libraries used by
kernel-doc.py, when excecuted via the build system or via
scripts/find-unused-docs.sh.
Reported-by: Andy Shevchenko
Closes: https://lore.kernel.org/linu
Em Mon, 21 Apr 2025 10:35:29 -0600
Jonathan Corbet escreveu:
> Dmitry Baryshkov writes:
>
> > On Wed, Apr 16, 2025 at 03:51:03PM +0800, Mauro Carvalho Chehab wrote:
> >>
> >> As reported by Andy, the Kernel build system runs kernel-doc script for
> >> DRM,
> >> when W=1. Due to Python's nor
As reported by Andy, the Kernel build system runs kernel-doc script for DRM,
when W=1. Due to Python's normal behavior, its JIT compiler will create
a bytecode and store it under scripts/lib/*/__pycache__. As one may be using
O= and even having the sources on a read-only mount point, disable its
c
To all X.Org Foundation Members:
The election for the X.Org Foundation Board of Directors will begin on
30 April 2025. We have five candidates who are running for four seats.
They are (in alphabetical order):
* Andres Gomez
* Arkadiusz Hiler
* Megan Knight
* Lyude Paul
* Harry Wentland
Atta
On Wed, Apr 23, 2025 at 06:30:48PM +0900, Akira Yokosawa wrote:
> On Tue, 22 Apr 2025 10:57:33 +0300, Andy Shevchenko wrote:
> > On Mon, Apr 21, 2025 at 10:35:29AM -0600, Jonathan Corbet wrote:
> >> Dmitry Baryshkov writes:
[...]
> >> > Would it be possible to properly support O= and create pyc
+ Harry and Leo
On Wed, Apr 16, 2025 at 2:33 AM Borah, Chaitanya Kumar
wrote:
>
> Hello Alexander,
>
> > -Original Message-
> > From: Murthy, Arun R
> > Sent: Monday, April 7, 2025 11:14 AM
> > To: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; intel-
> > x...@lists.fr
Hi Nitin
On Wed Apr 16, 2025 at 10:36 AM UTC, Nitin Gote wrote:
> Sometimes engine reset fails because the engine resumes from an
> incorrect RING_HEAD. Engine head failed to set to zero even after
> writing into it. This is a timing issue and we experimented
> different values and found out that
On Wed, Apr 23, 2025 at 06:23:34PM +0530, Arun R Murthy wrote:
> Minimum HBlank is programmed to address jitter for high resolutions with
> high refresh rates that have small Hblank, specifically where Hblank is
> smaller than one MTP.
The log could've mentioned what the patch actually does (at le
== Series Details ==
Series: Rework/Correction on minimum hblank calculation (rev5)
URL : https://patchwork.freedesktop.org/series/147361/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16451 -> Patchwork_147361v5
Summary
--
On Mon, Mar 24, 2025 at 02:29:37PM +0100, Andi Shyti wrote:
When setting the CCS mode, we mistakenly used wa_masked_en() to
apply the workaround, which reads from the register and masks the
existing value with the new one.
That's not what wa_masked_* does. The use of wa_masked* depends if the
r
== Series Details ==
Series: Rework/Correction on minimum hblank calculation (rev5)
URL : https://patchwork.freedesktop.org/series/147361/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Rework/Correction on minimum hblank calculation (rev5)
URL : https://patchwork.freedesktop.org/series/147361/
State : warning
== Summary ==
Error: dim checkpatch failed
23f27b87e286 drm/display/dp: Export fn to calculate link symbol cycles
63582b51e068 drm/i915/dis
On Thu, Mar 27, 2025 at 12:40:01AM +0100, Andi Shyti wrote:
The CCS engine workaround was previously added in a section
shared by both RCS and CCS engines.
Move it to the proper CCS-specific section so that it's applied
only once, avoiding unintended duplication caused by the first
CCS/RCS detec
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/display: Ensure enough lines
between delayed VBlank and VBlank
URL : https://patchwork.freedesktop.org/series/148127/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16451 -> Patchwork_148127v1
On Thu, Mar 27, 2025 at 12:40:05AM +0100, Andi Shyti wrote:
From: Andi Shyti
The I915_ENGINE_FIRST_RENDER_COMPUTE flag is no longer used.
Its purpose has been replaced by the FIRST_CCS() helper, which
determines the first render or compute engine as needed.
which is not true since you impleme
On Thu, Mar 27, 2025 at 12:39:59AM +0100, Andi Shyti wrote:
Hi,
While testing the multi-CCS static load balancing, Arshad
discovered that the CCS workaround was being applied twice, due
to commit [*].
Further discussions with Lucas led to rethinking the purpose of
I915_ENGINE_FIRST_RENDER_COMPU
On Wed, Apr 23, 2025 at 06:23:33PM +0530, Arun R Murthy wrote:
> Unify the function to calculate the link symbol cycles for both dsc and
> non-dsc case and export the function so that it can be used in the
> respective platform display drivers for other calculations.
>
> v2: unify the fn for both
On 4/23/2025 6:47 PM, Nautiyal, Ankit K wrote:
On 4/21/2025 9:18 PM, Mitul Golani wrote:
From: Ville Syrjälä
Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mitul Golani
---
== Series Details ==
Series: Rework/Correction on minimum hblank calculation (rev4)
URL : https://patchwork.freedesktop.org/series/147361/
State : warning
== Summary ==
Error: dim checkpatch failed
db70d168974e drm/display/dp: Export fn to calculate link symbol cycles
ab0b24489b70 drm/i915/dis
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/reg: use REG_BIT and friends to
define DP registers
URL : https://patchwork.freedesktop.org/series/148125/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16451 -> Patchwork_148125v1
===
On 4/21/2025 9:18 PM, Mitul Golani wrote:
From: Ville Syrjälä
Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c |
== Series Details ==
Series: Rework/Correction on minimum hblank calculation (rev4)
URL : https://patchwork.freedesktop.org/series/147361/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16451 -> Patchwork_147361v4
Summary
--
Unify the function to calculate the link symbol cycles for both dsc and
non-dsc case and export the function so that it can be used in the
respective platform display drivers for other calculations.
v2: unify the fn for both dsc and non-dsc case (Imre)
v3: rename drm_dp_link_symbol_cycles to drm_d
Signed-off-by: Arun R Murthy
---
Changes in v5:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v4:
https://lore.kernel.org/r/20250423-hblank-v4-0-8e513cc54...@intel.com
Changes in v5:
- EDITME: describe what is new in this
Minimum HBlank is programmed to address jitter for high resolutions with
high refresh rates that have small Hblank, specifically where Hblank is
smaller than one MTP.
TODO: Add the min_hblank calculation for hdmi as well.
v2: move from intel_audio.c to intel_dp.c
some correction in link_bpp_x
== Series Details ==
Series: Rework/Correction on minimum hblank calculation (rev4)
URL : https://patchwork.freedesktop.org/series/147361/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 4/23/2025 3:51 PM, Jani Nikula wrote:
On Wed, 23 Apr 2025, "Nautiyal, Ankit K" wrote:
On 4/21/2025 9:18 PM, Mitul Golani wrote:
Add state checker for dc balance params. Also add macro to
check source support.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.
On Wed, 2025-04-23 at 14:53 +0530, Animesh Manna wrote:
> Make a generic alpm enable function for sink which can be used for
> PSR2/PR/Lobf.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 25
> ++-
> drivers/gpu/drm/i915/display/intel_psr
On Wed, 2025-04-23 at 14:53 +0530, Animesh Manna wrote:
> Simplify the alpm check which will be used multiple places like
> source configuration, sink enablement etc.
Reviewed-by: Jouni Högander
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 5 +++--
> dri
== Series Details ==
Series: LOBF enablement fix (rev10)
URL : https://patchwork.freedesktop.org/series/141974/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_16450 -> Patchwork_141974v10
Summary
---
**SUCCESS**
No
On Wed, 2025-04-23 at 14:53 +0530, Animesh Manna wrote:
> For every commit the dependent condition for LOBF is checked
> and accordingly update has_lobf flag which will be used
> to update the ALPM_CTL register during commit.
>
> v1: Initial version.
> v2: Avoid reading h/w register without has_lo
To deterministically capture the transition of the state machine going from
SRDOFFACK to IDLE, the delayed V. Blank should be at least one line after
the non-delayed V. Blank.
Ensure this by adding new interface into intel_psr to query number of lines
needed for vblank delay and call it from intel
Logical place for PSR workaround needing vblank delay is in
intel_psr_min_vblank_delay. Move it there.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display.c | 12
drivers/gpu/drm/i915/display/intel_psr.c | 11 ++-
2 files changed, 10 insertions(+
Define the DP register contents using the REG_BIT, REG_GENMASK,
etc. macros. Ditch the unhelpful comments. Rename eDP related register
content macros to have EDP_ prefix.
Reviewed-by: Suraj Kandpal
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/g4x_dp.c | 23 +++--
drivers/gpu/drm
On Wed, 23 Apr 2025, "Nautiyal, Ankit K" wrote:
> On 4/21/2025 9:18 PM, Mitul Golani wrote:
>> Add state checker for dc balance params. Also add macro to
>> check source support.
>>
>> Signed-off-by: Mitul Golani
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 7 +++
>> drivers/g
== Series Details ==
Series: LOBF enablement fix (rev10)
URL : https://patchwork.freedesktop.org/series/141974/
State : warning
== Summary ==
Error: dim checkpatch failed
b53ba73df55c drm/i915/alpm: use variable from intel_crtc_state instead of
intel_psr
52016359761f drm/i915/lobf: Add lobf e
== Series Details ==
Series: LOBF enablement fix (rev10)
URL : https://patchwork.freedesktop.org/series/141974/
State : warning
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/141974/revisions/10/mbox/ not
found
Minimum HBlank is programmed to address jitter for high resolutions with
high refresh rates that have small Hblank, specifically where Hblank is
smaller than one MTP.
TODO: Add the min_hblank calculation for hdmi as well.
v2: move from intel_audio.c to intel_dp.c
some correction in link_bpp_x
On Tue, 2025-04-22 at 08:28 +, Kahola, Mika wrote:
> > -Original Message-
> > From: Intel-gfx On Behalf
> > Of Jouni
> > Högander
> > Sent: Monday, 14 April 2025 13.05
> > To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> > Cc: Hogander, Jouni
> > Subject: [PATCH v
Add/remove some blank lines to/from i915_reg.h primarily to help the
scripted refactoring coming up, separating unrelated registers and
keeping the comments together.
v2: Also add some extra blank lines
Reviewed-by: Suraj Kandpal # v1
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_re
Enablement of LOBF is added in post plane update whenever
has_lobf flag is set. As LOBF can be enabled in non-psr
case as well so adding in post plane update. There is no
change of configuring alpm with psr path.
v1: Initial version.
v2: Use encoder-mask to find the associated encoder from
crtc-st
Unify the function to calculate the link symbol cycles for both dsc and
non-dsc case and export the function so that it can be used in the
respective platform display drivers for other calculations.
v2: unify the fn for both dsc and non-dsc case (Imre)
v3: rename drm_dp_link_symbol_cycles to drm_d
Signed-off-by: Arun R Murthy
---
Changes in v5:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v4:
https://lore.kernel.org/r/20250422-hblank-v4-0-bdb7bd9c4...@intel.com
Changes in v3:
- EDITME: describe what is new in this ser
Disable LOBF/ALPM for any erroneous condition from sink side.
v1: Initial version.
v2: Add centralized alpm error handling. [Jouni]
v3: Improve debug print. [Jouni]
v4: Disable alpm permanently for sink error. [Jouni]
Signed-off-by: Animesh Manna
Reviewed-by: Jouni Högander
---
drivers/gpu/drm
Simplify the alpm check which will be used multiple places like
source configuration, sink enablement etc.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 5 +++--
drivers/gpu/drm/i915/display/intel_psr.c | 6 ++
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
Make a generic alpm enable function for sink which can be used for
PSR2/PR/Lobf.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 25 ++-
drivers/gpu/drm/i915/display/intel_psr.c | 23 -
2 files changed, 24 insertions(+), 24 de
The ALPM_CTL can be updated from different context, so
add mutex to sychonize the update.
Signed-off-by: Animesh Manna
Reviewed-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_alpm.c | 11 ++-
drivers/gpu/drm/i915/display/intel_alpm.h | 2 +-
drivers/gpu/drm
Add an interface in debugfs which will help in debugging LOBF
feature.
v1: Initial version.
v2:
- Remove FORCE_EN flag. [Jouni]
- Change prefix from I915 to INTEL. [Jani]
- Use u8 instead of bool for lobf-debug flag. [Jani]
v3:
- Use intel_connector instead of display. [Jani]
- Remove edp connecto
For every commit the dependent condition for LOBF is checked
and accordingly update has_lobf flag which will be used
to update the ALPM_CTL register during commit.
v1: Initial version.
v2: Avoid reading h/w register without has_lobf check. [Jani]
v3: Update LOBF in post plane update instead of sep
Currently clearing of alpm registers is done through psr_disable()
which is always not correct, without psr also alpm can exist. So
dis-integrate alpm_disable() from psr_disable().
v1: Initial version.
v2:
- Remove h/w register read from alpm_disable(). [Jani]
Signed-off-by: Animesh Manna
Review
LOBF can be enabled with vrr fixed rate mode, so add check
if vmin = vmax = flipline in compute_config().
Signed-off-by: Animesh Manna
Reviewed-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_alpm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/i
Lobf is enabled part of ALPM configuration and if has_lobf
is set to true respective bit for LOBF will be set. Add debug
print while setting the bitfield of LOBF.
Signed-off-by: Animesh Manna
Reviewed-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_alpm.c | 6 +-
1 file changed, 5
From: Jouni Högander
Currently code is making assumption that PSR is enabled when
intel_alpm_configure is called. This doesn't work if alpm is configured
before PSR is enabled.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 4 ++--
1 f
v1: Initial version.
v2: Addressed review comments from Jani.
v3: Addressed review comments from Jouni.
v4: Addressed review comments received on v3.
v5: Addressed review comments received on v4.
v6: Addressed review comments received on v5.
v7: Addressed review comments received on v6.
v8: Address
Remove the last uses of struct drm_i915_private from intel_hdmi.c, and
drop the dependency on i915_drv.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel
A milestone, with this all the intel_de_*() users pass in struct
intel_display, and we can remove the compat wrappers. \o/
Jani Nikula (3):
drm/i915/dpt: convert intel_dpt_common.c to struct intel_display
drm/i915/hdmi: convert rest of intel_hdmi.c to struct intel_display
drm/i915/de: drop d
All the users of intel_de_*() functions now pass in struct
intel_display, and we can remove the __to_intel_display() _Generic()
compat wrappers.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_de.h | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --gi
Remove the last uses of struct drm_i915_private from intel_dpt_common.c,
and drop the dependency on i915_drv.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dpt_common.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/
On 4/21/2025 9:18 PM, Mitul Golani wrote:
Add state dump for dc balance params to track dc balance
crtc state config.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 9 -
1 file changed, 8 insertions(+), 1 del
On 4/21/2025 9:19 PM, Mitul Golani wrote:
enable dc balance from vrr compute config when vrr is
s/enable/Enable
enabled in adaptive vtotal mode
Nitpick: Add fullstop.
With above fixed:
Reviewed-by: Ankit Nautiyal
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vr
On 4/21/2025 9:18 PM, Mitul Golani wrote:
Prepare state check param for enabling dc balance enable bit.
This patch can be squashed into the previous patch.
Regards,
Ankit
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/
On 4/21/2025 9:18 PM, Mitul Golani wrote:
Add state checker for dc balance params. Also add macro to
check source support.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +++
drivers/gpu/drm/i915/display/intel_vrr.c | 20 +++-
2 f
On 4/21/2025 9:18 PM, Mitul Golani wrote:
From: Ville Syrjälä
Pause the DMC DC balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mitul Golani
---
drivers/gpu/dr
On 4/21/2025 9:18 PM, Mitul Golani wrote:
From: Ville Syrjälä
Add function to control DC balance enable/disable bit via DSB.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dmc.c | 24 +
On 4/21/2025 9:18 PM, Mitul Golani wrote:
From: Ville Syrjälä
Add vblank evasion logic when vrr is already enabled along with
dc balance is computed.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dsb.c
On 4/21/2025 9:18 PM, Mitul Golani wrote:
From: Ville Syrjälä
Initialise delayed vblank position for evasion logic.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vblank.c | 13 +
1 file chang
On 4/21/2025 9:18 PM, Mitul Golani wrote:
From: Ville Syrjälä
Refactor vmin/vmax functions for better computation.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 41 +++-
1 file changed, 19 insertions(+), 22 de
On 4/21/2025 9:18 PM, Mitul Golani wrote:
Add compute config for DC balance params. This will be required
to calculate correct balance requirement for DMC firmware.
Subject can simply be Compute DC balance parameters.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.
On 4/21/2025 9:18 PM, Mitul Golani wrote:
Add enable/disable calls along with required hw registers
for DC balance enablement.
Signed-off-by: Mitul Golani
---
.../drm/i915/display/intel_display_types.h| 7 ++
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 71 +++
dri
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