== Series Details ==
Series: drm/i915/dmc_wl: Introduce debugfs interface
URL : https://patchwork.freedesktop.org/series/143696/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15979 -> Patchwork_143696v1
Summary
---
*
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Move shutdown sequences
under display driver
URL : https://patchwork.freedesktop.org/series/143698/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubc
== Series Details ==
Series: drm/i915/dmc_wl: Introduce debugfs interface
URL : https://patchwork.freedesktop.org/series/143696/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dmc_wl: Introduce debugfs interface
URL : https://patchwork.freedesktop.org/series/143696/
State : warning
== Summary ==
Error: dim checkpatch failed
6c801299b19b drm/i915/dmc_wl: Pass offset instead of reg to range table iterator
86fa0b28b846 drm/i915/dmc
On Fri, Jan 17, 2025 at 10:20:17PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 09, 2025 at 09:31:37AM +0200, Jouni Högander wrote:
> > Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
> > usage also when PSR is enabled for LunarLake onwards.
>
> We seem to still lack an ans
== Series Details ==
Series: drm/i915/slpc: Add sysfs for SLPC power profiles (rev5)
URL : https://patchwork.freedesktop.org/series/142685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15979 -> Patchwork_142685v5
Summary
-
== Series Details ==
Series: drm/i915/slpc: Add sysfs for SLPC power profiles (rev5)
URL : https://patchwork.freedesktop.org/series/142685/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
This aligns with the current i915 display sequence.
Cc: Maarten Lankhort
Reviewed-by: Jonathan Cavitt
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/xe/display/xe_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/driv
Move display related shutdown sequences from i915_driver to
intel_display_driver.
No functional change. Just taking the right ownership and
start some reconciliation of them between i915 and Xe.
v2: - Add missing _nogem caller (Imre)
- Fix comment style (Jonathan)
v3: rebase
Cc: Imre Deak
R
Start the xe-i915-display reconciliation by using the same
shutdown sequences.
v2: include the stubs for !CONFIG_DRM_XE_DISPLAY (Kunit)
Reviewed-by: Jonathan Cavitt
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/xe/display/xe_display.c | 48 +++--
drivers/gpu/drm/xe/displa
== Series Details ==
Series: drm/i915/slpc: Add sysfs for SLPC power profiles (rev4)
URL : https://patchwork.freedesktop.org/series/142685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15979 -> Patchwork_142685v4
Summary
-
The DMC wakelock code needs to keep track of register offsets that need
the wakelock for proper access. If one of the necessary offsets are
missed, then the failure in asserting the wakelock is very likely to
cause problems down the road.
A miss could happen for at least two different reasons:
-
We use a spinlock to protect DMC wakelock debugfs data, since it is also
accessed by the core DMC wakelock logic. Taking the spinlock when the
debugfs is not in use introduces a small but unnecessary penalty.
Since the debugfs functionality is only expected to be used for, uh,
debugging sessions,
We already have a way of finding the set of untracked offsets for which
there has been one or more MMIO operations via the
"intel_dmc_wl/untracked" debugfs interface.
However, in order to try adding one or more of those registers to the
set of tracked offsets, one would need to manually change the
The DMC wakelock code needs to keep track of register offsets that need
the wakelock for proper access. If one of the necessary offsets are
missed, then the failure in asserting the wakelock is very likely to
cause problems down the road.
A miss could happen for at least two different reasons:
-
We will add another function that checks the offset in an upcoming
change. Instead of passing the reg variable to only extract the offset
later, let's extract the offset before so that we do not need to repeat
ourselves.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_dmc_wl.
Default SLPC power profile is Base(0). Power Saving mode(1)
has conservative up/down thresholds and is suitable for use with
apps that typically need to be power efficient.
Selected power profile will be displayed in this format-
$ cat slpc_power_profile
[base]power_saving
$ echo power_sa
== Series Details ==
Series: drm/i915/slpc: Add sysfs for SLPC power profiles (rev4)
URL : https://patchwork.freedesktop.org/series/142685/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/slpc: Add sysfs for SLPC power profiles (rev4)
URL : https://patchwork.freedesktop.org/series/142685/
State : warning
== Summary ==
Error: dim checkpatch failed
649d91b5a09b drm/i915/slpc: Add sysfs for SLPC power profiles
-:97: CHECK:PARENTHESIS_ALIGNMENT
On Fri, Jan 17, 2025 at 12:24:14PM -0800, Vinay Belgaumkar wrote:
> Default SLPC power profile is Base(0). Power Saving mode(1)
> has conservative up/down thresholds and is suitable for use with
> apps that typically need to be power efficient.
>
> Selected power profile will be displayed in this
Default SLPC power profile is Base(0). Power Saving mode(1)
has conservative up/down thresholds and is suitable for use with
apps that typically need to be power efficient.
Selected power profile will be displayed in this format-
$ cat slpc_power_profile
[base]power_saving
$ echo power_sa
On Thu, Jan 09, 2025 at 09:31:37AM +0200, Jouni Högander wrote:
> Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
> usage also when PSR is enabled for LunarLake onwards.
We seem to still lack an answer as to when the PSR wakes, when it
latches the update, and how does al
On Thu, Jan 09, 2025 at 09:31:33AM +0200, Jouni Högander wrote:
> Allow writing PSR2_MAN_TRK_CTL using DSB by using intel_de_write_dsb. Do
> not check intel_dp->psr.lock being held when using DSB. This assertion
> doesn't make sense as in case of using DSB the actual write happens later
> and we ar
On Fri, Jan 17, 2025 at 10:21:53AM -0800, Belgaumkar, Vinay wrote:
>
> On 1/17/2025 6:29 AM, Rodrigo Vivi wrote:
> > On Thu, Jan 16, 2025 at 03:51:03PM -0800, Belgaumkar, Vinay wrote:
> > > On 1/16/2025 2:57 PM, Rodrigo Vivi wrote:
> > > > On Fri, Jan 10, 2025 at 03:21:51PM -0800, Vinay Belgaumkar
== Series Details ==
Series: drm/xe/dp: Fix non-display builds with DP tunnelling incorrectly enabled
URL : https://patchwork.freedesktop.org/series/143678/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15978 -> Patchwork_143678v1
==
On 1/17/2025 6:29 AM, Rodrigo Vivi wrote:
On Thu, Jan 16, 2025 at 03:51:03PM -0800, Belgaumkar, Vinay wrote:
On 1/16/2025 2:57 PM, Rodrigo Vivi wrote:
On Fri, Jan 10, 2025 at 03:21:51PM -0800, Vinay Belgaumkar wrote:
Default SLPC power profile is Base(0). Power Saving mode(1)
has conservativ
== Series Details ==
Series: drm/xe/dp: Fix non-display builds with DP tunnelling incorrectly enabled
URL : https://patchwork.freedesktop.org/series/143678/
State : warning
== Summary ==
Error: dim checkpatch failed
9fe9fde0fb60 drm/xe/dp: Fix non-display builds with DP tunnelling incorrectly
Hi Nitin,
...
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 070ab6546987..686ed33c1a8b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1146,7 +1146,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>
Hi Nitin,
...
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index c910168602d2..14fdaf675636 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -96,7 +96,7 @@ u32 intel_crtc_ma
Hi Nitin,
On 2025-01-14 at 00:13:16 GMT, Nitin Gote wrote:
> Fix all typos in files under drm/i915/soc reported by codespell tool.
>
> Signed-off-by: Nitin Gote
Reviewed-by: Krzysztof Niemiec
Thanks
Krzysztof
Hi Nitin,
On 2025-01-14 at 00:13:15 GMT, Nitin Gote wrote:
> Fix all typos in files under drm/i915/selftests reported by codespell tool.
>
> v2: Fix commenting style
>
> Signed-off-by: Nitin Gote
Reviewed-by: Krzysztof Niemiec
Thanks
Krzysztof
Hi Nitin,
On 2025-01-14 at 00:13:14 GMT, Nitin Gote wrote:
> Fix all typos in files under drm/i915/pxp reported by codespell tool.
>
> Signed-off-by: Nitin Gote
Reviewed-by: Krzysztof Niemiec
Thanks
Krzysztof
Hi Nitin,
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index b6d97da63d1f..621140a7fda3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -245,
Hi Nitin,
...
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 6439c8e91a8d..f8af9659653d 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -1924,7 +1924,7 @@ static int perform_bb_shadow(
Hi Nitin,
thanks for the series.
On 2025-01-14 at 00:13:11 GMT, Nitin Gote wrote:
> Fix all typos in files under drm/i915/gt reported by codespell tool.
>
> v2: Fix grammer mistake in comment
>
> Signed-off-by: Nitin Gote
Small nitpick - there's a typo in the commit log: "grammer" should be
On Fri, Jan 17, 2025 at 05:55:57PM +0200, Imre Deak wrote:
On Thu, Jan 16, 2025 at 02:38:34PM -0600, Lucas De Marchi wrote:
On Mon, Jan 13, 2025 at 07:40:59PM +0200, Imre Deak wrote:
> On Mon, Jan 13, 2025 at 06:38:34PM +0200, Jani Nikula wrote:
> > On Mon, 13 Jan 2025, Imre Deak wrote:
> > > E
On Thu, Jan 16, 2025 at 02:38:34PM -0600, Lucas De Marchi wrote:
> On Mon, Jan 13, 2025 at 07:40:59PM +0200, Imre Deak wrote:
> > On Mon, Jan 13, 2025 at 06:38:34PM +0200, Jani Nikula wrote:
> > > On Mon, 13 Jan 2025, Imre Deak wrote:
> > > > Enable the DP tunneling functionality in the xe driver.
Code for the DP tunnelling functionality in the xe driver can be
built only if the display code is also built, adjust the kconfig
dependency accordingly.
Cc: Suraj Kandpal
Fixes: 73900dce57e4 ("drm/xe/dp: Enable DP tunneling")
Reported-by: Lucas De Marchi
Signed-off-by: Imre Deak
---
drivers/g
On Mon, Jan 13, 2025 at 02:26:21PM -0500, Ed Maste wrote:
> On Wed, 13 Sept 2023 at 14:11, Shankar, Uma wrote:
> >
> > > From: Ville Syrjälä
> > >
> > > With all the known issues sorted out we can start to use DSB to load the
> > > LUTs.
>
> On FreeBSD with a port of the i915 driver from Linux
On Thu, Jan 16, 2025 at 03:51:03PM -0800, Belgaumkar, Vinay wrote:
>
> On 1/16/2025 2:57 PM, Rodrigo Vivi wrote:
> > On Fri, Jan 10, 2025 at 03:21:51PM -0800, Vinay Belgaumkar wrote:
> > > Default SLPC power profile is Base(0). Power Saving mode(1)
> > > has conservative up/down thresholds and is
On Thu, Jan 16, 2025 at 02:32:21PM -0600, Lucas De Marchi wrote:
> On Mon, Jan 13, 2025 at 05:48:32PM +0200, Imre Deak wrote:
> > Enable the DP tunneling functionality in the xe driver.
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_tunnel.h | 5 +++--
> > driv
On Tue, Jan 14, 2025 at 02:07:18PM +0200, Vinod Govindapillai wrote:
> Dirty rectangle feature allows FBC to recompress a subsection
> of a frame. When this feature is enabled, display will read
> the scan lines between dirty rectangle start line and dirty
> rectangle end line in subsequent frames.
On Tue, Jan 14, 2025 at 02:07:16PM +0200, Vinod Govindapillai wrote:
> If FBC is already active, we don't need to call FBC activate
> routine again during the post plane update. As this will
> explicitly call the nuke and also rewrite the FBC ctl registers.
> "intel_atomic_commit_tail-> intel_post_
On 1/17/2025 1:11 PM, Mitul Golani wrote:
High refresh rate panels which may have small line times
and vblank sizes, Check if vblank size is sufficient for
dsc prefill latency.
--v2:
- Consider chroma downscaling factor in latency calculation. [Ankit]
- Replace with appropriate function name.
On 1/17/2025 1:11 PM, Mitul Golani wrote:
High refresh rate panels which may have small line times
and vblank sizes, Check if vblank size is sufficient for
enabled scaler users.
--v2:
- Use hweight* family of functions for counting bits. [Jani]
- Update precision handling for hscale and vscale
== Series Details ==
Series: drm/i915: Handle vblank delay vs. fastboot and finish DSB plane update
enabling (rev2)
URL : https://patchwork.freedesktop.org/series/143633/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15974 -> Patchwork_143633v2
===
Hi CI Team,
On 2025-01-16 at 13:18:25 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/gt: Use spin_lock_irqsave() in interruptible context
> URL : https://patchwork.freedesktop.org/series/143600/
> State : failure
>
...
> Possible new issues
> ---
>
> Here
Quoting Gustavo Sousa (2025-01-13 17:38:55-03:00)
>Pipe interrupt registers live in their respective pipes' power wells,
>which are below PG0. That means that they must also be tracked as
>registers that are powered-off during dynamic DC states.
>
>For that, we first convert the display IRQ code to
== Series Details ==
Series: Check Scaler and DSC Prefill Latency Against Vblank (rev5)
URL : https://patchwork.freedesktop.org/series/143160/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15973 -> Patchwork_143160v5
Summar
== Series Details ==
Series: drm/i915/dp: Guarantee a minimum HBlank time (rev8)
URL : https://patchwork.freedesktop.org/series/139267/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/139267/revisions/8/mbox/ not
applied
Applying: drm/i915/dp: Guar
== Series Details ==
Series: Check Scaler and DSC Prefill Latency Against Vblank (rev5)
URL : https://patchwork.freedesktop.org/series/143160/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/incl
Hi,
> > > + guc_warn(guc, "excessive init time: [freq = %dMHz -> %dMHz vs
> > > %dMHz, perf_limit_reasons = 0x%08X]\n",
> > > + before_freq, intel_rps_read_actual_frequency(>->rps),
> > > + intel_rps_get_requested_frequency(>->rps),
> > While, -> is cle
On Wed, Jan 15, 2025 at 10:18:16PM -0800, Christoph Hellwig wrote:
> On Wed, Jan 15, 2025 at 11:31:35AM +0200, Kirill A. Shutemov wrote:
> > Now as PG_reclaim is gone, its name can be reclaimed for better
> > use :)
> >
> > Rename PG_dropbehind to PG_reclaim and rename all helpers around it.
>
>
On Wed, Jan 15, 2025 at 02:46:44PM -0700, Yu Zhao wrote:
> On Wed, Jan 15, 2025 at 2:35 PM Matthew Wilcox wrote:
> >
> > On Wed, Jan 15, 2025 at 11:31:29AM +0200, Kirill A. Shutemov wrote:
> > > -static void lru_deactivate_file(struct lruvec *lruvec, struct folio
> > > *folio)
> > > -{
> > > -
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