Hi Jani,
> -Original Message-
> From: Jani Nikula
> Sent: Tuesday, January 7, 2025 6:22 PM
> To: Gote, Nitin R ; intel-gfx@lists.freedesktop.org
> Cc: Shyti, Andi ; Gote, Nitin R
> Subject: Re: [PATCH v1 7/8] drm/i915/display: fix typos in i915/display files
>
> On Mon, 06 Jan 2025, Nit
Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
usage also when PSR is enabled for LunarLake onwards.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i9
Changing PSR mode using DSB is not implemented. Do not use DSB when PSR
mode is changing.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/g
Add new interface for checking possible PSR/PR mode change. We need this
information to decide if DSB can be used.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 20
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 22 insertion
Do needed changes to handle PSR2_MAN_TRK_CTL correctly when DSB is in use:
1. Write PSR2_MAN_TRK_CTL in commit_pipe_pre_planes only when not using
DSB.
2. Add PSR2_MAN_TRK_CTL writing into DSB commit in
intel_atomic_dsb_finish.
Taking PSR lock over DSB commit is not needed because PSR2_MAN_
Allow writing PSR2_MAN_TRK_CTL using DSB by using intel_de_write_dsb. Do
not check intel_dp->psr.lock being held when using DSB. This assertion
doesn't make sense as in case of using DSB the actual write happens later
and we are not taking intel_dp->psr.lock mutex over dsb commit.
Signed-off-by: J
In LunarLake we have SFF_CTL register which contains SFF bit ored with
respective SFF bit in PSR2_MAN_TRK_CTL register. Use this register instead
of the bit in PSR2_MAN_TRK_CTL on frontbuffer tracking callbacks. This
helps us avoiding taking psr mutex when performing atomic commit.
We don't need t
Add register definitions for SFF_CTL and CFF_CTL registers. Name them as
LNL_SFF_CTL and LNL_CFF_CTL.
v2: use _MMIO_TRANS instead of _MMIO_TRANS2
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drive
This is a clean-up and a preparation for adding own SFF and CFF registers
for LunarLake onwards.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 88 +---
1 file changed, 31 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/
We are preparing for a change where only frontbuffer flush will use
single full frame bit of a new register (SFF_CTL) available on LunarLake
onwards.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
psr_force_hw_tracking_exit is misleading name as it is used for PSR1, PSR2
HW tracking and PSR2 selective fetch. Due to this rename it as
intel_psr_force_update.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 8
1 file changed, 4 insertions(+), 4 deletions(
This patch set is doing necessary modifications to support PSR update
using DSB on LunarLake onwards
It is not necessary to wait for PSR1 to idle or PSR2 to exit DEEP
sleep at the begin of commit This is left out from DSB commit. There
might be room for optimization for non-DSB as well because suc
On Fri, 2025-01-03 at 14:41 -0300, Gustavo Sousa wrote:
> Pipe interrupt registers live in their respective pipes' power wells,
> which are below PG0. That means that they must also be tracked as
> registers that are powered-off during dynamic DC states.
>
> There are probably more ranges that we
On Fri, 2025-01-03 at 14:41 -0300, Gustavo Sousa wrote:
> Most of MMIO accesses from intel_display_irq.c are currently done via
> uncore_*() functions instead of the display-specific ones, namely
> intel_de_*(). Because of that, DMC wakelock ends up being ignored and
> some invalid MMIO accesses ar
On Wed, 08 Jan 2025 13:19:16 -0800, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Wed, Jan 08, 2025 at 11:30:59AM -0800, Dixit, Ashutosh wrote:
> > On Wed, 08 Jan 2025 11:11:53 -0800, Belgaumkar, Vinay wrote:
> > >
> > >
> > > On 1/8/2025 6:13 AM, Rodrigo Vivi wrote:
> > > > The Balancer and DCC strateg
== Series Details ==
Series: drm/i915/cx0_phy: Update HDMI TMDS C20 algorithm value (rev5)
URL : https://patchwork.freedesktop.org/series/141280/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15926 -> Patchwork_141280v5
Sum
On 1/8/2025 6:31 AM, Abel Vesa wrote:
Link Training Tunable PHY Repeaters (LTTPRs) are defined in DisplayPort
1.4a specification. As the name suggests, these PHY repeaters are
capable of adjusting their output for link training purposes.
According to the DisplayPort standard, LTTPRs have two
== Series Details ==
Series: drm/i915/cx0_phy: Update HDMI TMDS C20 algorithm value (rev5)
URL : https://patchwork.freedesktop.org/series/141280/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/cx0_phy: Update HDMI TMDS C20 algorithm value (rev5)
URL : https://patchwork.freedesktop.org/series/141280/
State : warning
== Summary ==
Error: dim checkpatch failed
dbfd52a793e2 drm/i915/display: Add MTL subplatforms definition
-:70: ERROR:COMPLEX_MACRO:
On 1/8/2025 6:31 AM, Abel Vesa wrote:
According to the DisplayPort standard, LTTPRs have two operating
modes:
- non-transparent - it replies to DPCD LTTPR field specific AUX
requests, while passes through all other AUX requests
- transparent - it passes through all AUX requests.
Switc
On Wed, Jan 08, 2025 at 12:16:50PM +1100, Stephen Rothwell wrote:
> Hi All,
>
> On Mon, 6 Jan 2025 13:03:48 +1100 Stephen Rothwell
> wrote:
> >
> > Today's linux-next merge of the drm-intel tree got a conflict in:
> >
> > drivers/gpu/drm/i915/display/intel_display_driver.c
> >
> > between co
On Wed, Jan 08, 2025 at 12:41:21PM +0200, Jani Nikula wrote:
> Going forward, struct intel_display is the main device data structure
> for display. Switch to it.
>
> For MISSING_CASE(), log the PCI ID instead of the platform. This removes
> the final INTEL_INFO() usage from display.
>
> Signed-of
On Wed, Jan 08, 2025 at 12:41:20PM +0200, Jani Nikula wrote:
> Arguably it's a display property whether it's impacted by GPU reset. And
> we don't have to look at i915 device info from display.
I think everything was so mixed together back on those early platforms
that it's hard to really separate
On Wed, Jan 08, 2025 at 11:30:59AM -0800, Dixit, Ashutosh wrote:
> On Wed, 08 Jan 2025 11:11:53 -0800, Belgaumkar, Vinay wrote:
> >
> >
> > On 1/8/2025 6:13 AM, Rodrigo Vivi wrote:
> > > The Balancer and DCC strategies were left off on a fear that
> > > these strategies would conflict with the i915
On Wed, Jan 08, 2025 at 12:41:19PM +0200, Jani Nikula wrote:
> Add a helper for checking the gpu_reset_clobbers_display flag to make it
> easier to relocate the flag later.
>
> We keep the intel_gt_gpu_reset_clobbers_display() helper to not have to
> duplicate the gt -> display pointer chase.
>
>
On Wed, Jan 08, 2025 at 12:41:18PM +0200, Jani Nikula wrote:
> Add a helper for checking the gpu_reset_clobbers_display flag to make it
> easier to relocate the flag later.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> driv
On Wed, Jan 08, 2025 at 12:41:17PM +0200, Jani Nikula wrote:
> pending_fb_pin is more about display than GPU reset. Move it to struct
> intel_display. The restore sub-struct already contains reset related
> members, so move it there.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
> ---
== Series Details ==
Series: drm/i915/display: Don't update DBUF_TRACKER_STATE_SERVICE (rev3)
URL : https://patchwork.freedesktop.org/series/142892/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15924 -> Patchwork_142892v3
On Wed, Jan 08, 2025 at 12:41:16PM +0200, Jani Nikula wrote:
> Going forward, struct intel_display will be the main display device
> structure. Convert display reset to it as much as possible.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
Although this patch does make me wonder: is "g
On Thu, Jan 09, 2025 at 01:32:10AM +0530, Ravi Kumar Vodapalli wrote:
> The bspec only asks the driver to reprogram the DBUF_CTL's
> DBUF_TRACKER_STATE_SERVICE field to 0x8 on DG2 and platforms with
> display version 12. All other platforms should avoid reprogramming
> this register at driver init.
The bspec only asks the driver to reprogram the DBUF_CTL's
DBUF_TRACKER_STATE_SERVICE field to 0x8 on DG2 and platforms with
display version 12. All other platforms should avoid reprogramming
this register at driver init.
Although we've been accidentally reprogramming DBUF_CTL on platforms
where t
On Wed, 08 Jan 2025 11:11:53 -0800, Belgaumkar, Vinay wrote:
>
>
> On 1/8/2025 6:13 AM, Rodrigo Vivi wrote:
> > The Balancer and DCC strategies were left off on a fear that
> > these strategies would conflict with the i915's waitboost.
> > However, these strategies are only active in certain condit
On 1/8/2025 6:13 AM, Rodrigo Vivi wrote:
The Balancer and DCC strategies were left off on a fear that
these strategies would conflict with the i915's waitboost.
However, these strategies are only active in certain conditions where
the system is TDP limited. So, they don't conflict, but help the
On 1/8/2025 6:13 AM, Rodrigo Vivi wrote:
Let's peak on the Balancer and DCC status, now that we
are using the default strategies.
s/peak/peek
v2: fix identation
Cc: Vinay Belgaumkar
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 17 +
1 fi
On Wed, Jan 08, 2025 at 05:30:20PM +, Patchwork wrote:
Hi CI team,
the failure is unrelated to changes, see below.
Thanks,
Imre
> == Series Details ==
>
> Series: drm/i915/dp_mst: Fix error handling/clean up pointer use
> URL : https://patchwork.freedesktop.org/series/143259/
> State : f
Hi Dave, Sima,
Just one fix this week - a revert to unbreak HDCP compliance.
Should be fine but with a disclaimer that no testing happened. It appears
CI is on fire due rc6 being severely broken somewhere in the vmstat code.
Which dumps a large warning on boot in the whole CI farm.
Tvrtko
drm
== Series Details ==
Series: drm/i915/dp_mst: Fix error handling/clean up pointer use
URL : https://patchwork.freedesktop.org/series/143259/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15924 -> Patchwork_143259v1
Summary
On Wed, 08 Jan 2025, Imre Deak wrote:
> Simplify getting a drm_device pointer when using to_i915() in
> intel_dp_mst.c from the already available intel_display object, instead
> of getting it from a DRM KMS object.
>
> While at it rename dev_priv to i915, following the driver's standard
> terminol
On 1/8/2025 8:06 PM, Dnyaneshwar Bhadane wrote:
There is new field "edp pipe joiner feature" size of 2 bytes in the
eDP VBT block. Each bit represent panel number to be enable/disable
for this feature.
Default value:
For ARL platform, 0x to keep the feature disabled by default.
Xe3lpd on
== Series Details ==
Series: drm/dp: Rework LTTPR transparent mode handling and add support to msm
driver
URL : https://patchwork.freedesktop.org/series/143251/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15924 -> Patchwork_143251v1
=
On Wed, Jan 08, 2025 at 08:04:58AM +0200, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Deak, Imre
> > Sent: Tuesday, January 7, 2025 8:33 PM
> > To: Kandpal, Suraj
> > Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > Nautiyal,
> > Ankit K ; Shankar
On Wed, 08 Jan 2025, Imre Deak wrote:
> Use the driver's standard intel_display::platform.alderlake_p instead of
> IS_ALDERLAKE_P().
>
> Signed-off-by: Imre Deak
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions
On Wed, 08 Jan 2025, Imre Deak wrote:
> Simplify the use of to_intel_display() in intel_dp_mst.c passing it the
> already available intel_connector pointer, instead of looking up a
> drm_device pointer for the same purpose.
>
> Suggested-by: Jani Nikula
> Signed-off-by: Imre Deak
I guess I woul
On Wed, 08 Jan 2025, Dnyaneshwar Bhadane wrote:
> There is new field "edp pipe joiner feature" size of 2 bytes in the
> eDP VBT block. Each bit represent panel number to be enable/disable
> for this feature.
>
> Default value:
> For ARL platform, 0x to keep the feature disabled by default.
> X
== Series Details ==
Series: drm/i915/bios: Define eDP pipe joiner feature for VBT
URL : https://patchwork.freedesktop.org/series/143256/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15924 -> Patchwork_143256v1
Summary
---
== Series Details ==
Series: drm/dp: Rework LTTPR transparent mode handling and add support to msm
driver
URL : https://patchwork.freedesktop.org/series/143251/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separatel
== Series Details ==
Series: Enable GuC SLPC default balancing strategies (rev3)
URL : https://patchwork.freedesktop.org/series/142676/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15924 -> Patchwork_142676v3
Summary
-
== Series Details ==
Series: drm/i915/audio: convert to struct intel_display
URL : https://patchwork.freedesktop.org/series/143248/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15924 -> Patchwork_143248v1
Summary
---
== Series Details ==
Series: drm/i915/audio: convert to struct intel_display
URL : https://patchwork.freedesktop.org/series/143248/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bit
Follow the canonical way in intel_dp_mst.c, referencing a connector only
via a struct intel_connector pointer and naming this pointer 'connector'
instead of 'intel_connector', the only exception being the casting of
a drm_connector function parameter pointer to intel_connector, calling
the drm_conn
After an error during adding an MST connector the MST port and the
intel_connector object could be leaked, fix this up.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
dif
Use the driver's standard intel_display::platform.alderlake_p instead of
IS_ALDERLAKE_P().
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm
Simplify getting a drm_device pointer when using to_i915() in
intel_dp_mst.c from the already available intel_display object, instead
of getting it from a DRM KMS object.
While at it rename dev_priv to i915, following the driver's standard
terminology.
Suggested-by: Jani Nikula
Signed-off-by: Im
Simplify the use of to_intel_display() in intel_dp_mst.c passing it the
already available intel_connector pointer, instead of looking up a
drm_device pointer for the same purpose.
Suggested-by: Jani Nikula
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +++---
1 fi
This patchset contains unapplied changes from [1], fixing an error
handling path while adding an MST connector and cleaning up the
intel_connector vs. drm_connector pointer use in intel_dp_mst.c,
addressing the review comments from Jani.
It also uses the driver's standard intel_display::platform.a
== Series Details ==
Series: drm/i915/audio: convert to struct intel_display
URL : https://patchwork.freedesktop.org/series/143248/
State : warning
== Summary ==
Error: dim checkpatch failed
8e88d7bd097b drm/i915/audio: convert to struct intel_display
48a81ac0fa0d drm/i915/audio: convert LPE a
LTTPRs operating modes are defined by the DisplayPort standard and the
generic framework now provides a helper to switch between them, which
is handling the explicit disabling of non-transparent mode and its
disable->enable sequence mentioned in the DP Standard v2.0 section
3.6.6.1.
So use the new
LTTPRs operating modes are defined by the DisplayPort standard and the
generic framework now provides a helper to switch between them, which
is handling the explicit disabling of non-transparent mode and its
disable->enable sequence mentioned in the DP Standard v2.0 section
3.6.6.1.
So use the new
There is new field "edp pipe joiner feature" size of 2 bytes in the
eDP VBT block. Each bit represent panel number to be enable/disable
for this feature.
Default value:
For ARL platform, 0x to keep the feature disabled by default.
Xe3lpd onwards, 0x to keep the feature enable by default by
Link Training Tunable PHY Repeaters (LTTPRs) are defined in DisplayPort
1.4a specification. As the name suggests, these PHY repeaters are
capable of adjusting their output for link training purposes.
According to the DisplayPort standard, LTTPRs have two operating
modes:
- non-transparent - it re
According to the DisplayPort standard, LTTPRs have two operating
modes:
- non-transparent - it replies to DPCD LTTPR field specific AUX
requests, while passes through all other AUX requests
- transparent - it passes through all AUX requests.
Switching between this two modes is done by the DPT
Looking at both i915 and nouveau DP drivers, both are setting the first
LTTPR (if found) in transparent mode first and then in non-transparent
mode, just like the DP v2.0 specification mentions in section 3.6.6.1.
Being part of the standard, setting the LTTPR in a specific operation mode
can be ea
On Sat, 04 Jan 2025, Gustavo Sousa wrote:
> Next version of [1], with review comments addressed.
>
> Note that I have added one extra "squash patch", because I was not sure that
> was
> the correct way of handling sanitization and thought that having it separate
> would make it easier for reviewe
Let's peak on the Balancer and DCC status, now that we
are using the default strategies.
v2: fix identation
Cc: Vinay Belgaumkar
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i9
Although in most of the cases it will be a lot faster, there are some
rare cases in a few platforms where this can result in a timeout,
specially when we enable the GPU-CPU balancing in GuC SLPC.
The wait by itself consumes CPU and the GPU workload is small enough,
so the priority is given to the C
The Balancer and DCC strategies were left off on a fear that
these strategies would conflict with the i915's waitboost.
However, these strategies are only active in certain conditions where
the system is TDP limited. So, they don't conflict, but help the
waitboost by guaranteeing a bit more of GT f
The goal here is to improve the GPU performance in some cases
where we are TDP limited, with both GPU and CPU with high
utilization and PCODE without power to fulfill both sides.
Of course, only matters for integrated parts with GuC
SLPC enabled: ADL and MTL.
Apparently the ADL on our CI was not h
On Mon, 2025-01-06 at 09:45 +0530, Animesh Manna wrote:
> Disable LOBF/ALPM for any erroneous condition from sink side.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 38
> +++
> drivers/gpu/drm/i915/display/intel_alpm.h | 1 +
> ...
Going forward, struct intel_display will be the main display device
structure. Convert intel_audio.[ch] to it. Do some minor checkpatch
fixes while at it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c| 413 +-
drivers/gpu/drm/i915/display/intel_aud
The intel prefix is more accurate for display stuff. Rename.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c | 82 +++---
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/d
Going forward, struct intel_display will be the main display device
structure. Convert intel_lpe_audio.[ch] to it. Do some minor checkpatch
fixes while at it.
TODO: Not sure if irq_set_chip_data(irq, dev_priv); is used.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c
Audio conversion to intel display.
Jani Nikula (3):
drm/i915/audio: convert to struct intel_display
drm/i915/audio: convert LPE audio to struct intel_display
drm/i915/audio: rename function prefixes from i915 to intel
drivers/gpu/drm/i915/display/intel_audio.c| 487 +-
On Wed, 08 Jan 2025, "Hogander, Jouni" wrote:
> On Mon, 2025-01-06 at 09:45 +0530, Animesh Manna wrote:
>> Add an interface in debugfs which will help in debugging LOBF
>> feature.
>>
>> Signed-off-by: Animesh Manna
>> ---
>> drivers/gpu/drm/i915/display/intel_alpm.c | 51
>>
On Mon, Dec 30, 2024 at 02:24:45PM +, Krzysztof Karas wrote:
> Hi Apoorva and Andi,
>
> > > Initialize rq to NULL to prevent uninitialized pointer reads.
> >
> > where is it happening?
> >
> > Andi
>
> There are two instances that I see:
> 1) err = fn(..., &rq); <- this probably will set th
== Series Details ==
Series: Check Scaler and DSC Prefill Latency Against Vblank (rev2)
URL : https://patchwork.freedesktop.org/series/143160/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15923 -> Patchwork_143160v2
Summar
On 25-01-08 15:11:50, Dmitry Baryshkov wrote:
> On Mon, Jan 06, 2025 at 02:45:48PM +0200, Abel Vesa wrote:
> > On 25-01-03 20:09:42, Dmitry Baryshkov wrote:
> > > On Fri, Jan 03, 2025 at 02:58:17PM +0200, Abel Vesa wrote:
> > > > LTTPRs operating modes are defined by the DisplayPort standard and th
On 25-01-07 10:30:29, Johan Hovold wrote:
> On Fri, Jan 03, 2025 at 02:58:15PM +0200, Abel Vesa wrote:
> > According to the DisplayPort standard, LTTPRs have two operating
> > modes:
> > - non-transparent - it replies to DPCD LTTPR field specific AUX
> >requests, while passes through all other
%40intel.com
patch subject: [PATCH v3 3/5] drm/i915/scaler: Compute scaling factors for pipe
scaler
config: x86_64-randconfig-161-20250107
(https://download.01.org/0day-ci/archive/20250108/202501080440.cxe0zhxj-...@intel.com/config)
compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project
== Series Details ==
Series: Check Scaler and DSC Prefill Latency Against Vblank (rev2)
URL : https://patchwork.freedesktop.org/series/143160/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/incl
On Mon, Jan 06, 2025 at 02:45:48PM +0200, Abel Vesa wrote:
> On 25-01-03 20:09:42, Dmitry Baryshkov wrote:
> > On Fri, Jan 03, 2025 at 02:58:17PM +0200, Abel Vesa wrote:
> > > LTTPRs operating modes are defined by the DisplayPort standard and the
> > > generic framework now provides a helper to swi
On Mon, 2025-01-06 at 09:45 +0530, Animesh Manna wrote:
> Add an interface in debugfs which will help in debugging LOBF
> feature.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 51
> +++
> .../drm/i915/display/intel_display_types.h |
> -Original Message-
> From: Intel-xe On Behalf Of Nemesa
> Garg
> Sent: Thursday, 26 December 2024 8.07
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Garg, Nemesa ; Vandita Kulkarni
>
> Subject: [PATCH] drm/i915/display: Add WA_14018221282
>
> It was observ
On Mon, 2025-01-06 at 09:45 +0530, Animesh Manna wrote:
> For every commit the dependent condition for LOBF is checked
> and accordingly update has_lobf flag which will be used
> to update the ALPM_CTL register during commit.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/
== Series Details ==
Series: drm/i915: Add VM_DONTEXPAND to exported buffers
URL : https://patchwork.freedesktop.org/series/143237/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15923 -> Patchwork_143237v1
Summary
---
Compute scaling factors and scaler user for pipe scaler if
particular scaler user is pipe scaler.
--v2:
- Update typo 'plane scaling' to 'pipe scaling'. [Ankit]
- Remove FIXME tag which was added to check for pipe scaling
factors as well. [Ankit]
- Should be common hscale, vscale instead of local
Limit downscaling to less than 1.5 (source/destination) in
the horizontal direction and 1.0 in the vertical direction,
When configured for Pipe YUV 420 encoding for port output.
Bspec: 50441
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/skl_scaler.c | 10 ++
1 file change
Check if vblank is sufficient for dsc prefill latency.
--v2:
- Consider chroma downscaling factor in latency calculation. [Ankit]
- Replace with appropriate function name.
--v3:
- Remove FIXME tag.[Ankit]
- Replace Ycbcr444 to Ycbcr420.[Anit]
- Correct precision. [Ankit]
- Use some local valiable
Check if vblank is too short for scaler prefill latency.
--v2:
- Use hweight* family of functions for counting bits. [Jani]
- Update precision handling for hscale and vscale. [Ankit]
- Consider chroma downscaling factor during latency
calculation. [Ankit]
- Replace function name from scaler_prefil
Add scaling factors to scaler_state for a particular scaler user.
These factors will be used later to compute scaler prefill latency.
Currently, only plane scaling factors are stored, but the same members
can later be extended to store pipe scaling factors as well.
--v2:
- Rephrase commit message
Compute and check if dsc and scaler prefill latency is sufficient with
respect to vblank.
Previous Revision Reference:
https://patchwork.freedesktop.org/series/141203/
https://patchwork.freedesktop.org/series/142745/
Mitul Golani (7):
drm/i915/scaler: Add and compute scaling factors
drm/i915/
Refactor max scaling factor computation into a reusable
function for scalers.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/skl_scaler.c | 63 ---
1 file changed, 34 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
b/drive
Pass crtc_state to intel_atomic_setup_scaler, this will help to
check if pch_pfit enabled or not and also will be useful to pass
scaler_state with the same which will be used later to store
hscale and vscale values.
-- v2:
- Commit message updates. parse to pass. (Ankit)
Signed-off-by: Mitul Gola
== Series Details ==
Series: drm/i915: Add VM_DONTEXPAND to exported buffers
URL : https://patchwork.freedesktop.org/series/143237/
State : warning
== Summary ==
Error: dim checkpatch failed
f720c3aac1d7 drm/i915: Add VM_DONTEXPAND to exported buffers
-:75: WARNING:MISSING_FIXES_TAG: The commi
== Series Details ==
Series: drm/i915/psr: clarify intel_psr_pre_plane_update() conditions
URL : https://patchwork.freedesktop.org/series/143235/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15923 -> Patchwork_143235v1
Sum
== Series Details ==
Series: drm/i915: display reset cleanups
URL : https://patchwork.freedesktop.org/series/143233/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15922 -> Patchwork_143233v1
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: display reset cleanups
URL : https://patchwork.freedesktop.org/series/143233/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
drm_gem_mmap_obj() expects VM_DONTEXPAND flag to be set after mmap
callback is executed. Set this flag at the end of i915_gem_dmabuf_mmap()
to prevent WARN on mmap in buffers imported from i915 e.g.,
[ 283.623215] WARNING: CPU: 1 PID: 12693 at drivers/gpu/drm/drm_gem.c:1087
drm_gem_mmap_obj+0x19
Add a helper for checking the gpu_reset_clobbers_display flag to make it
easier to relocate the flag later.
We keep the intel_gt_gpu_reset_clobbers_display() helper to not have to
duplicate the gt -> display pointer chase.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_displa
Try to make GPU and display reset slightly more better separated,
convert to intel_display, stop INTEL_INFO() usage from display.
Jani Nikula (6):
drm/i915/display: convert display reset to struct intel_display *
drm/i915: move pending_fb_pin to struct intel_display
drm/i915: add intel_gt_gp
Make the conditions easier to follow. We don't do anything for
!psr->enabled, so hoist psr->enabled check higher, avoiding all the
checks when !psr->enabled. Stop the bitwise OR abuse on booleans by
removing the temporary variable altogether.
Cc: Jouni Högander
Cc: Suraj Kandpal
Reviewed-by: Jou
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