> -Original Message-
> From: Intel-gfx On Behalf Of
> Patchwork
> Sent: Friday, December 20, 2024 10:52 AM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org
> Subject: ✗ Fi.CI.BUILD: failure for Revert "drm/i915/hdcp: Don't enable
> HDCP1.4 directly from check_link"
>
> == Ser
== Series Details ==
Series: drm/i915/dp: Guarantee a minimum HBlank time (rev5)
URL : https://patchwork.freedesktop.org/series/139267/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15896 -> Patchwork_139267v5
Summary
-
== Series Details ==
Series: drm/i915/dp: Guarantee a minimum HBlank time (rev5)
URL : https://patchwork.freedesktop.org/series/139267/
State : warning
== Summary ==
Error: dim checkpatch failed
6a6116420c7b drm/i915/dp: Guarantee a minimum HBlank time
-:67: WARNING:LONG_LINE: line length of 1
== Series Details ==
Series: Clean and Optimise mtl_ddi_prepare_link_retrain
URL : https://patchwork.freedesktop.org/series/143080/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15896 -> Patchwork_143080v1
Summary
---
Mandate a minimum Hblank symbol cycle count between BS and BE in 8b/10b
MST and 128b/132b mode.
v2: Affine calculation/updation of min HBlank to dp_mst (Jani)
v3: moved min_hblank from struct intel_dp to intel_crtc_state (Jani)
v4: use max/min functions, change intel_xx *intel_xx to intel_xx *xx
> -Original Message-
> From: Intel-xe On Behalf Of Arun R
> Murthy
> Sent: Friday, January 3, 2025 10:43 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCH v5] drm/i915/dp: Guarantee a minimum HBlank time
>
> Mandate a minimu
Use IS_ENABLED() instead of defined() for checking whether a kconfig
option is enabled.
Nitin Gote (1):
drm/i915/gt: Prefer IS_ENABLED() instead of defined() on config option
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.25.1
Use IS_ENABLED() instead of defined() for checking whether a kconfig
option is enabled.
Signed-off-by: Nitin Gote
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/
On Tue, Dec 17, 2024 at 09:36:52PM +0530, Vignesh Raman wrote:
> Uprev IGT to the latest version and update expectation files.
>
> Signed-off-by: Vignesh Raman
> ---
>
> v1:
> - Pipeline link -
> https://gitlab.freedesktop.org/vigneshraman/linux/-/pipelines/1327810
> Will update the flake
> -Original Message-
> From: Intel-xe On Behalf Of Ankit
> Nautiyal
> Sent: Friday, January 3, 2025 8:44 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; jani.nik...@linux.intel.com; Deak, Imre
>
> Subject: [PATCH] drm/i915/dp: Return early if dsc is requi
Mandate a minimum Hblank symbol cycle count between BS and BE in 8b/10b
MST and 128b/132b mode.
Spec: DP2.1a
v2: Affine calculation/updation of min HBlank to dp_mst (Jani)
v3: moved min_hblank from struct intel_dp to intel_crtc_state (Jani)
v4: use max/min functions, change intel_xx *intel_xx to i
> -Original Message-
> From: Murthy, Arun R
> Sent: Friday, January 3, 2025 10:39 AM
> To: Kandpal, Suraj ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCHv4] drm/i915/dp: Guarantee a minimum HBlank time
>
> > > -Original Message-
> > > F
A small optimization and cleanup for mtl_port_buf_ctl_program function
which lets use intel_de_rmw instead of a intel_de_read and
intel_de_write.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_ddi.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a
Use intel display instead of drm_i915_private in
mtl_ddi_prepare_link_retrain & mtl_port_buf_ctl_program
functions.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_ddi.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm
While going through code of mtl_ddi_prepare_link_retrain which calls
mtl_port_buf_ctl_program I saw some potential cleanup and optimization
that could take place i.e the i915 to intel_display usage and using
intel_de_rmw instead of the intel_de_read, add mask and then
intel_de_write sequence. This
== Series Details ==
Series: drm/i915/dp: Return early if dsc is required but not supported
URL : https://patchwork.freedesktop.org/series/143077/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15896 -> Patchwork_143077v1
Su
> > -Original Message-
> > From: Intel-xe On Behalf Of
> > Arun R Murthy
> > Sent: Monday, November 11, 2024 2:56 PM
> > To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Murthy, Arun R
> > Subject: [PATCHv4] drm/i915/dp: Guarantee a minimum HBlank time
> >
> > M
Currently, when bandwidth is insufficient for a given mode, we attempt
to use DSC. This is indicated by a debug print, followed by a check for
DSC support.
The debug message states that we are trying DSC, but DSC might not be
supported, which can give an incorrect picture in the logs if we bail
ou
On Mon, 2024-12-23 at 18:53 +0100, Thomas Hellstrom wrote:
> Hi Dave, Simona
>
> The Xe fixes for -rc5.
This PR just got superseded by a new one (drm-xe-fixes-2025-01-02),
that includes also the commits mentioned here.
Thanks,
Thomas
>
> Thanks,
> Thomas
>
> drm-xe-fixes-2024-12-23:
> UAPI
Hi Dave, Simona!
Happy new year!
This PR supersedes the one sent out 24-12-23, since that didn't seem to get
pulled over the holidays. There's one extra commit (The OA fixes). The
rest of the summary is repeated.
Thanks,
Thomas
drm-xe-fixes-2025-01-02:
This supersedes drm-xe-fixes-2024-12-23.
U
On Thu, Dec 19, 2024 at 11:34:01PM +0200, Jani Nikula wrote:
> Add ACT handling for 128b/132b SST.
>
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 13 +
> 1 file c
On Thu, Dec 19, 2024 at 11:34:05PM +0200, Jani Nikula wrote:
> Enable basic 128b/132b SST functionality without compression. Reuse
> intel_dp_mtp_tu_compute_config() to figure out the TU after we've
> determined we need to use an UHBR rate.
>
> It's slightly complicated as the M/N computation is d
On Thu, Dec 19, 2024 at 11:34:04PM +0200, Jani Nikula wrote:
> 128b/1232b SST will have mst_master_transcoder set and matching
> cpu_transcoder. Ensure disable also for 128b/132b SST.
>
> Co-developed-by: Imre Deak
> Signed-off-by: Imre Deak
> Signed-off-by: Jani Nikula
Reviewed-by: Imre Deak
On Thu, Dec 19, 2024 at 11:34:03PM +0200, Jani Nikula wrote:
> We'll only ever get here in MST mode from MST stream encoders; the
> primary encoder's ->get_config() won't be called when we've detected
> it's MST.
>
> v2: Read mst_master_transcoder in 128b/132b SST path (Imre)
>
> Signed-off-by: J
On Thu, Dec 19, 2024 at 11:34:02PM +0200, Jani Nikula wrote:
> We'll want to distinguish 128b/132b SST and MST modes at state
> readout. There's a catch, though. From the hardware perspective,
> 128b/132b SST and MST programming are pretty much the same. And we can't
> really ask the sink at this p
== Series Details ==
Series: drm/i915/display: handle hdmi connector init failures, and no HDMI/DP
cases (rev7)
URL : https://patchwork.freedesktop.org/series/142119/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15892_full -> Patchwork_142119v7_full
=
> > GSC NVM controller HW errors on quad access overlapping 1K border.
> > Align 64bit read and write to avoid readq/writeq over 1K border.
> >
> > Acked-by: Miquel Raynal
> > Signed-off-by: Alexander Usyskin
> > ---
> > drivers/mtd/devices/mtd-intel-dg.c | 35
> ++
>
On Thu, Jan 02, 2025 at 12:52:38PM +0200, Jani Nikula wrote:
> On Tue, 31 Dec 2024, Imre Deak wrote:
> > On Thu, Dec 19, 2024 at 11:33:59PM +0200, Jani Nikula wrote:
> >> Write the payload allocation table for 128b/132b SST. Use VCPID 1 and
> >> start from slot 0, with dp_m_n.tu slots.
> >>
> >>
Hi,
https://patchwork.freedesktop.org/series/142119/
i915.CI.BAT - Re-reported.
Thanks,
Ravali.
-Original Message-
From: I915-ci-infra On Behalf Of
Jani Nikula
Sent: 02 January 2025 16:47
To: i915-ci-in...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ i915.C
On Thu, Jan 02, 2025 at 12:30:34PM +0200, Jani Nikula wrote:
> On Tue, 31 Dec 2024, Imre Deak wrote:
> > On Thu, Dec 19, 2024 at 11:33:56PM +0200, Jani Nikula wrote:
> >> Handle 128b/132b SST in intel_dp_mtp_tu_compute_config(). The remote
> >> bandwidth overhead and time slot allocation are only
== Series Details ==
Series: drm/i915/selftest: Change throttle criteria for rps
URL : https://patchwork.freedesktop.org/series/143060/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15892_full -> Patchwork_143060v1_full
Sum
> ...
>
> > +struct intel_dg_nvm {
> > + struct kref refcnt;
> > + void __iomem *base;
> > + size_t size;
> > + unsigned int nregions;
> > + struct {
> > + const char *name;
> > + u8 id;
> > + u64 offset;
> > + u64 size;
> > + } regions[];
>
> _
== Series Details ==
Series: drm/i915/dp: 128b/132b uncompressed SST (rev3)
URL : https://patchwork.freedesktop.org/series/142547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15892_full -> Patchwork_142547v3_full
Summary
== Series Details ==
Series: drm/i915/display: handle hdmi connector init failures, and no HDMI/DP
cases (rev7)
URL : https://patchwork.freedesktop.org/series/142119/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15892 -> Patchwork_142119v7
===
On Thu, Jan 02, 2025 at 11:39:07AM +0200, Jani Nikula wrote:
> On Tue, 31 Dec 2024, Imre Deak wrote:
> > On Thu, Dec 19, 2024 at 11:34:00PM +0200, Jani Nikula wrote:
> >> Write the DP2 specific VFREQ registers.
> >>
> >> This is preparation for enabling 128b/132b SST. This path is not
> >> reacha
On Thu, 02 Jan 2025, Jani Nikula wrote:
> The struct drm_dp_mst_topology_mgr *mgr parameter is only used for debug
> logging in case the passed in link rate or lane count are zero. There's
> no further error checking as such, and the function returns 0.
>
> There should be no case where the parame
== Series Details ==
Series: drm/i915/selftest: Change throttle criteria for rps
URL : https://patchwork.freedesktop.org/series/143060/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15892 -> Patchwork_143060v1
Summary
-
On Mon, 30 Dec 2024, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display: handle hdmi connector init failures, and no HDMI/DP
> cases (rev7)
> URL : https://patchwork.freedesktop.org/series/142119/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_15892 -
On Tue, 2024-12-31 at 10:08 -0300, Gustavo Sousa wrote:
> Quoting Hogander, Jouni (2024-12-31 08:23:58-03:00)
> > On Tue, 2024-12-24 at 13:53 -0300, Gustavo Sousa wrote:
> > > The CMTG is a timing generator that runs in parallel with
> > > transcoders
> > > timing generators and can be used as a re
Current live_rps_control() implementation errors out on throttling.
This was done with the assumption that throttling to minimum frequency
is a catastrophic failure, which is incorrect. Throttling can happen
due to variety of reasons and often times out of our control. Also,
the resulting frequency
== Series Details ==
Series: drm/i915/dp: 128b/132b uncompressed SST (rev3)
URL : https://patchwork.freedesktop.org/series/142547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15892 -> Patchwork_142547v3
Summary
---
On Tue, 31 Dec 2024, Imre Deak wrote:
> On Thu, Dec 19, 2024 at 11:33:59PM +0200, Jani Nikula wrote:
>> Write the payload allocation table for 128b/132b SST. Use VCPID 1 and
>> start from slot 0, with dp_m_n.tu slots.
>>
>> This is preparation for enabling 128b/132b SST. This path is not
>> reach
>
> > @@ -89,6 +281,13 @@ static int intel_dg_mtd_probe(struct
> auxiliary_device *aux_dev,
> > goto err;
> > }
> >
> > + ret = intel_dg_nvm_init(nvm, device);
> > + if (ret < 0) {
> > + dev_err(device, "cannot initialize nvm\n");
> > + ret = -ENODEV;
>
> W
== Series Details ==
Series: drm/i915/dp: 128b/132b uncompressed SST (rev3)
URL : https://patchwork.freedesktop.org/series/142547/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dp: 128b/132b uncompressed SST (rev3)
URL : https://patchwork.freedesktop.org/series/142547/
State : warning
== Summary ==
Error: dim checkpatch failed
8c415b084cef drm/mst: remove mgr parameter and debug logging from
drm_dp_get_vc_payload_bw()
65dac07c52
Le 01/01/2025 à 16:39, Alexander Usyskin a écrit :
Add auxiliary driver for intel discrete graphics
non-volatile memory device.
CC: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
Le 01/01/2025 à 16:39, Alexander Usyskin a écrit :
In intel-dg, there is no access to the spi controller,
the information is extracted from the descriptor region.
CC: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
== Series Details ==
Series: PSR DSB support (rev2)
URL : https://patchwork.freedesktop.org/series/142520/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15892_full -> Patchwork_142520v2_full
Summary
---
**SUCCESS**
On Tue, 31 Dec 2024, Imre Deak wrote:
> On Thu, Dec 19, 2024 at 11:33:56PM +0200, Jani Nikula wrote:
>> Handle 128b/132b SST in intel_dp_mtp_tu_compute_config(). The remote
>> bandwidth overhead and time slot allocation are only relevant for MST;
>> SST only needs the local bandwidth and a check t
On Tue, 31 Dec 2024, Imre Deak wrote:
> On Thu, Dec 19, 2024 at 11:33:55PM +0200, Jani Nikula wrote:
>> Extract intel_dp_mtp_tu_compute_config() for figuring out the TU. Move
>> the link configuration and mst state access to the callers. This will be
>> easier to adapt to 128b/132b SST.
>>
>> v2:
The struct drm_dp_mst_topology_mgr *mgr parameter is only used for debug
logging in case the passed in link rate or lane count are zero. There's
no further error checking as such, and the function returns 0.
There should be no case where the parameters are zero. The returned
value is generally use
On Tue, 31 Dec 2024, Imre Deak wrote:
> On Thu, Dec 19, 2024 at 11:34:00PM +0200, Jani Nikula wrote:
>> Write the DP2 specific VFREQ registers.
>>
>> This is preparation for enabling 128b/132b SST. This path is not
>> reachable yet.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i9
== Series Details ==
Series: PSR DSB support (rev2)
URL : https://patchwork.freedesktop.org/series/142520/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15892 -> Patchwork_142520v2
Summary
---
**SUCCESS**
No regre
== Series Details ==
Series: PSR DSB support (rev2)
URL : https://patchwork.freedesktop.org/series/142520/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unr
== Series Details ==
Series: PSR DSB support (rev2)
URL : https://patchwork.freedesktop.org/series/142520/
State : warning
== Summary ==
Error: dim checkpatch failed
a26c90abb484 drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update
ca70087cd57a drm/i915/psr: Rename psr_force_hw_
Hi Dave, Simona,
Happy newyear!
Cheers,
~Maarten
drm-misc-fixes-2025-01-02:
drm-misc-fixes for v6.13-rc6:
- Only fixes for adv7511 driver, including a use-after-free.
The following changes since commit 1b684ca15f9d78f45de3cdba7e19611387e16aa7:
drm/sched: Fix drm_sched_fini() docu generation (
This is a clean-up and a preparation for adding own SFF and CFF registers
for LunarLake onwards.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 88 +---
1 file changed, 31 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/
In LunarLake we have SFF_CTL register which contains SFF bit ored with
respective SFF bit in PSR2_MAN_TRK_CTL register. Use this register instead
of the bit in PSR2_MAN_TRK_CTL on frontbuffer tracking callbacks. This
helps us avoiding taking psr mutex when performing atomic commit.
We don't need t
Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
usage also when PSR is enabled for LunarLake onwards.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i9
We have different approach on how flip is considered being complete. We are
waiting for vblank on DSB and generate interrupt when it happens and this
interrupt is considered as indication of completion -> we definitely do not
want to skip vblank wait.
Also not skipping scanline wait shouldn't caus
Add register definitions for SFF_CTL and CFF_CTL registers. Name them as
LNL_SFF_CTL and LNL_CFF_CTL.
v2: use _MMIO_TRANS instead of _MMIO_TRANS2
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drive
Do needed changes to handle PSR2_MAN_TRK_CTL correctly when DSB is in use:
1. Write PSR2_MAN_TRK_CTL in commit_pipe_pre_planes only when not using
DSB.
2. Add PSR2_MAN_TRK_CTL writing into DSB commit in
intel_atomic_dsb_finish.
Taking PSR lock over DSB commit is not needed because PSR2_MAN_
Allow writing PSR2_MAN_TRK_CTL using DSB by using intel_de_write_dsb. Do
not check intel_dp->psr.lock being held when using DSB. This assertion
doesn't make sense as in case of using DSB the actual write happens later
and we are not taking intel_dp->psr.lock mutex over dsb commit.
Signed-off-by: J
psr_force_hw_tracking_exit is misleading name as it is used for PSR1, PSR2
HW tracking and PSR2 selective fetch. Due to this rename it as
intel_psr_force_update.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 8
1 file changed, 4 insertions(+), 4 deletions(
This patch set is doing necessary modifications to support PSR update
using DSB on LunarLake onwards
It is not necessary to wait for PSR1 to idle or PSR2 to exit DEEP
sleep at the begin of commit This is left out from DSB commit. There
might be room for optimization for non-DSB as well because suc
We are preparing for a change where only frontbuffer flush will use
single full frame bit of a new register (SFF_CTL) available on LunarLake
onwards.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
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