Quoting Jani Nikula (2024-12-31 13:27:40-03:00)
>Going forward, struct intel_display is the main display device
>structure. Convert intel_global_state.[ch] to it.
>
>This allows us to make intel_pmdemand.c completely independent of
>i915_drv.h.
>
>Cc: Gustavo Sousa
>Signed-off-by: Jani Nikula
Re
Quoting Jani Nikula (2024-12-31 13:27:39-03:00)
>Going forward, struct intel_display is the main display device
>structure. Convert pmdemand to it.
>
>Cc: Gustavo Sousa
>Signed-off-by: Jani Nikula
Reviewed-by: Gustavo Sousa
with git show -W --word-diff and trust in the compiler.
>---
> .../dr
Quoting Jani Nikula (2024-12-31 13:27:38-03:00)
>Only intel_pmdemand.c should look inside the struct
>intel_pmdemand_state. Indeed, this is already the case. Finish the job
>and make struct intel_pmdemand_state opaque, preventing any direct pokes
>at the guts of it in the future.
>
>Cc: Gustavo Sou
Quoting Jani Nikula (2024-12-31 13:27:37-03:00)
>In preparation for making struct intel_pmdemand_state an opaque type,
>convert to_intel_pmdemand_state() to a function.
>
>Cc: Gustavo Sousa
>Signed-off-by: Jani Nikula
This looks good to me, so
Reviewed-by: Gustavo Sousa
, but I'm also taking
Quoting Jani Nikula (2024-12-31 08:45:56-03:00)
>On Tue, 24 Dec 2024, Gustavo Sousa wrote:
>> The CMTG is a timing generator that runs in parallel with transcoders
>> timing generators and can be used as a reference for synchronization.
>>
>> On PTL (display Xe3_LPD), we have observed that we are
== Series Details ==
Series: drm/i915/pmdemand: cleanups
URL : https://patchwork.freedesktop.org/series/143040/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15892 -> Patchwork_143040v1
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915/pmdemand: cleanups
URL : https://patchwork.freedesktop.org/series/143040/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, Dec 19, 2024 at 11:34:00PM +0200, Jani Nikula wrote:
> Write the DP2 specific VFREQ registers.
>
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 12
> 1 fil
On Thu, Dec 19, 2024 at 11:34:00PM +0200, Jani Nikula wrote:
> Write the DP2 specific VFREQ registers.
>
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 12
> 1 fil
On Thu, Dec 19, 2024 at 11:33:59PM +0200, Jani Nikula wrote:
> Write the payload allocation table for 128b/132b SST. Use VCPID 1 and
> start from slot 0, with dp_m_n.tu slots.
>
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet. Indeed, we don't yet compute TU for
Going forward, struct intel_display is the main display device
structure. Convert pmdemand to it.
Cc: Gustavo Sousa
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_driver.c | 4 +-
.../drm/i915/display/intel_display_power.c| 4 +-
.../drm/i915/display/intel_modeset_s
Going forward, struct intel_display is the main display device
structure. Convert intel_global_state.[ch] to it.
This allows us to make intel_pmdemand.c completely independent of
i915_drv.h.
Cc: Gustavo Sousa
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bw.c | 3 +-
Only intel_pmdemand.c should look inside the struct
intel_pmdemand_state. Indeed, this is already the case. Finish the job
and make struct intel_pmdemand_state opaque, preventing any direct pokes
at the guts of it in the future.
Cc: Gustavo Sousa
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i
In preparation for making struct intel_pmdemand_state an opaque type,
convert to_intel_pmdemand_state() to a function.
Cc: Gustavo Sousa
Signed-off-by: Jani Nikula
---
This is the simplest change. There could be other alternatives.
Outside of intel_pmdemand.c, this is only used to convert
dis
Make pmdemand state opaque, convert pmdemand and global state to struct
intel_display, and make pmdemand independent of i915_drv.h.
This is what I'd like to be done to all global state management. All
opaque, all converted to struct intel_display.
BR,
Jani.
Jani Nikula (4):
drm/i915/pmdemand:
On Thu, Dec 19, 2024 at 11:33:58PM +0200, Jani Nikula wrote:
> It's not very clearly specified, and the hardware bit is ill-named, but
> 128b/132b SST also needs the MST mode set in the DP_TP_CTL register.
>
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
>
> S
On Thu, Dec 19, 2024 at 11:33:57PM +0200, Jani Nikula wrote:
> 128b/132b SST needs 128b/132b mode enabled in the TRANS_DDI_FUNC_CTL
> register.
>
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet.
>
> v2: Use the MST path instead of SST to also set transport selec
On Thu, Dec 19, 2024 at 11:33:56PM +0200, Jani Nikula wrote:
> Handle 128b/132b SST in intel_dp_mtp_tu_compute_config(). The remote
> bandwidth overhead and time slot allocation are only relevant for MST;
> SST only needs the local bandwidth and a check that 64 slots isn't
> exceeded.
>
> Signed-o
On Thu, Dec 19, 2024 at 11:33:55PM +0200, Jani Nikula wrote:
> Extract intel_dp_mtp_tu_compute_config() for figuring out the TU. Move
> the link configuration and mst state access to the callers. This will be
> easier to adapt to 128b/132b SST.
>
> v2: Don't add SST stuff here yet
>
> Signed-off-
On Thu, Dec 19, 2024 at 11:33:54PM +0200, Jani Nikula wrote:
> The crtc_state->pbn member is only used as a temporary variable within
> mst_stream_find_vcpi_slots_for_bpp(). Remove it as unnecessary.
>
> Suggested-by: Imre Deak
> Signed-off-by: Jani Nikula
Reviewed-by: Imre Deak
> ---
> driv
On Thu, Dec 19, 2024 at 11:33:53PM +0200, Jani Nikula wrote:
> The callers of mst_stream_find_vcpi_slots_for_bpp() don't need the
> returned slots for anything. On the contrary, they need to jump through
> hoops to just distinguish between success and failure. Just return 0
> instead of slots from
On Thu, Dec 19, 2024 at 11:33:52PM +0200, Jani Nikula wrote:
> intel_dp_mst_compute_m_n() doesn't need the connector. Remove the
> parameter.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +--
> 1 file changed, 1 insertion(+), 2
On Thu, Dec 19, 2024 at 11:33:51PM +0200, Jani Nikula wrote:
> intel_dp_mst_bw_overhead() doesn't need the connector. Remove the
> parameter.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
> 1 file changed, 2 insertions(+),
On Thu, Dec 19, 2024 at 11:33:50PM +0200, Jani Nikula wrote:
> The struct drm_dp_mst_topology_mgr *mgr parameter is only used for debug
> logging in case the passed in link rate or lane count are zero. There's
> no further error checking as such, and the function returns 0.
>
> There should be no
On 12/18/2024 11:06 PM, Ville Syrjala wrote:
From: Ville Syrjälä
I'm seeing underruns with these 64bpp YUV formats on TGL.
The weird details:
- only happens on pipe B/C/D SDR planes, pipe A SDR planes
seem fine, as do all HDR planes
- somehow CDCLK related, higher CDCLK allows for bigger
On Tue, 31 Dec 2024, "Vodapalli, Ravi Kumar"
wrote:
> On 12/13/2024 11:33 AM, Suraj Kandpal wrote:
>> Usually retimers take around 30 to 40ms to exit all devices from
>> sleep state. Extended wake timeout request helps to give additional
>> time by reading the DPCD register through which sink req
On Tue, 31 Dec 2024, Gustavo Sousa wrote:
> Quoting Jani Nikula (2024-12-30 09:58:31-03:00)
>>On Tue, 24 Dec 2024, Gustavo Sousa wrote:
>>> Quoting Ville Syrjala (2024-12-19 10:08:25-03:00)
From: Ville Syrjälä
Include the standard "[CRTC:...]" information in the scaler debugs
to
Quoting Hogander, Jouni (2024-12-31 08:23:58-03:00)
>On Tue, 2024-12-24 at 13:53 -0300, Gustavo Sousa wrote:
>> The CMTG is a timing generator that runs in parallel with transcoders
>> timing generators and can be used as a reference for synchronization.
>>
>> On PTL (display Xe3_LPD), we have obs
Quoting Jani Nikula (2024-12-30 09:58:31-03:00)
>On Tue, 24 Dec 2024, Gustavo Sousa wrote:
>> Quoting Ville Syrjala (2024-12-19 10:08:25-03:00)
>>>From: Ville Syrjälä
>>>
>>>Include the standard "[CRTC:...]" information in the scaler debugs
>>>to make life easier.
>>
>> Drive-by comment (and goin
On 12/13/2024 11:33 AM, Suraj Kandpal wrote:
Usually retimers take around 30 to 40ms to exit all devices from
sleep state. Extended wake timeout request helps to give additional
time by reading the DPCD register through which sink requests the
minimal amount of time required to wake the sink
On Tue, 24 Dec 2024, Gustavo Sousa wrote:
> The CMTG is a timing generator that runs in parallel with transcoders
> timing generators and can be used as a reference for synchronization.
>
> On PTL (display Xe3_LPD), we have observed that we are inheriting from
> GOP a display configuration with th
On Tue, 2024-12-24 at 13:53 -0300, Gustavo Sousa wrote:
> The CMTG is a timing generator that runs in parallel with transcoders
> timing generators and can be used as a reference for synchronization.
>
> On PTL (display Xe3_LPD), we have observed that we are inheriting
> from
> GOP a display confi
On Fri, 2024-12-20 at 11:34 +0200, Ville Syrjälä wrote:
> On Fri, Dec 13, 2024 at 08:35:23AM +0200, Jouni Högander wrote:
> > Bspec says this for SFF/CFF:
> >
> > "Hardware samples this bit on the start of every V. Blank Guardband
> > region. For deterministic behavior, Software should ensure it i
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