> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, December 19, 2024 9:32 PM
> To: Garg, Nemesa
> Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/i915/display: After joiner compute pfit_dst
>
> On Thu, Dec 12, 2024 at 08:03:2
== Series Details ==
Series: Revert "drm/i915/hdcp: Don't enable HDCP1.4 directly from check_link"
URL : https://patchwork.freedesktop.org/series/142871/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
CC [M]
This reverts commit 483f7d94a0453564ad9295288c0242136c5f36a0.
This needs to be reverted since HDCP even after updating the connector
state HDCP property we don't reenable HDCP until the next commit
in which the CP Property is set causing compliance to fail.
Signed-off-by: Suraj Kandpal
---
drive
Hi all,
After merging the drm-misc tree, today's linux-next build (htmldocs)
produced these warnings:
drivers/gpu/drm/xlnx/zynqmp_dpsub.h:86: warning: Function parameter or struct
member 'audio' not described in 'zynqmp_dpsub'
drivers/gpu/drm/xlnx/zynqmp_dpsub.c:1: warning: no structured comment
On 20-12-2024 02:30, Rodrigo Vivi wrote:
sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.
VLK: 16314, 4304
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381
Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix
Add GT C6 and Frequency support. These will use the PMU interface
and are displayed per GT/device in the header.
GT: 0, c6: 94.54% req_freq: 750.63 MHz act_freq:0.00 MHz
GT: 1, c6: 2.75% req_freq: 1200.71 MHz act_freq: 1112.66 MHz
v2: Split patch into logical units and other review
commen
Functions to parse config ID and GT bit shift for PMU events.
Cc: Kamil Konieczny
Cc: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
lib/igt_perf.c | 68 ++
lib/igt_perf.h | 2 ++
2 files changed, 70 insertions(+)
diff --git a/lib/igt_perf.c
This will be used for gathering PMU event information.
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Signed-off-by: Vinay Belgaumkar
This will be used for gathering PMU event information.
Signed-off-by: Vinay Belgaumkar
/igt_debugfs.c.orig
---
lib/igt_drm_clients.c | 6 ++
l
Prep work for adding PMU support in gputop.
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Signed-off-by: Vinay Belgaumkar
---
tools/gputop.c | 28
1 file changed, 28 insertions(+)
diff --git a/tools/gputop.c b/tools/gputop.c
index 43b01f566..4e3663417
Use the PMU support being added in
https://patchwork.freedesktop.org/series/139121/ to add freq/c6 stats.
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Cc: Kamil Konieczny
Signed-off-by: Vinay Belgaumkar
Vinay Belgaumkar (4):
tools/gputop: Define data structs for PMU stats
lib/igt_drm_clients: Add
On 12/18/2024 11:27 AM, Kamil Konieczny wrote:
Hi Vinay,
On 2024-12-15 at 16:32:38 -0800, Vinay Belgaumkar wrote:
Add GT C6 and Frequency support. These will use the PMU interface
and are displayed per GT/device in the header.
GT: 0, c6: 94.54% req_freq: 750.63 MHz act_freq:0.00 MHz
GT:
== Series Details ==
Series: drm/i915/dmc_wl: Support extra values for dmc_wl_enable for debugging
URL : https://patchwork.freedesktop.org/series/142855/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15873 -> Patchwork_142855v1
=
== Series Details ==
Series: drm/i915/display: Reduce global state funcs boilerplate
URL : https://patchwork.freedesktop.org/series/142853/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15873 -> Patchwork_142853v1
Summary
-
-Original Message-
From: Intel-gfx On Behalf Of Gustavo
Sousa
Sent: Thursday, December 19, 2024 1:49 PM
To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
Cc: Ville Syrjälä ; Nikula, Jani
Subject: [PATCH 3/3] drm/i915/display: Use INTEL_GLOBAL_STATE_DEFAULTS
>
> Reduce
-Original Message-
From: Intel-gfx On Behalf Of Gustavo
Sousa
Sent: Thursday, December 19, 2024 1:49 PM
To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
Cc: Ville Syrjälä ; Nikula, Jani
Subject: [PATCH 2/3] drm/i915/display: Add infra to reduce global state funcs
boi
-Original Message-
From: Intel-xe On Behalf Of Gustavo
Sousa
Sent: Thursday, December 19, 2024 1:49 PM
To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
Cc: Ville Syrjälä ; Nikula, Jani
Subject: [PATCH 1/3] drm/i915/display: Do not assume zero offset when
duplicating
When debugging issues that might be related to the DMC wakelock code, it
might be useful to compare runs with the lock acquired while DC states
are enabled vs the regular case. If issues disappear with the former, it
might be a symptom of something wrong in our code. Support having this
"always loc
== Series Details ==
Series: drm/i915/display: Reduce global state funcs boilerplate
URL : https://patchwork.freedesktop.org/series/142853/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/display: Reduce global state funcs boilerplate
URL : https://patchwork.freedesktop.org/series/142853/
State : warning
== Summary ==
Error: dim checkpatch failed
ec99e692f6f4 drm/i915/display: Do not assume zero offset when duplicating
global state
b3d1fee
== Series Details ==
Series: drm/i915/dp: 128b/132b uncompressed SST (rev2)
URL : https://patchwork.freedesktop.org/series/142547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15873 -> Patchwork_142547v2
Summary
---
Currently, after sanitization, enable_dmc_wl will behave like a boolean
parameter (enabled vs disabled). However, in upcoming changes, we will
allow more values for debugging purposes. For that, let's make the
sanitized value an enumeration.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/
We already provide the value resulting from sanitization of
enable_dmc_wl in dmesg, however the reader will need to either have the
meanings memorized or look them up in the parameter's documentation.
Let's make things easier by providing a short human-readable name for
the parameter in dmesg.
Sig
When debugging issues that might be related to the DMC wakelock code, it
is sometimes useful to compare runs when we match any register offset vs
the regular case. If issues disappear when we take the wakelock for any
register, it might indicate that we are missing some offset to be
tracked. Suppor
This series adds support for two new values for dmc_wl_enable for
debugging purposes:
* 2 to mean "match any register", which makes the wakelock to be taken
for every display MMIO transaction;
* 3 to mean "always locked", which causes the lock to be taken as soon
as the DMC wakelock me
== Series Details ==
Series: drm/i915/dg1: Fix power gate sequence. (rev3)
URL : https://patchwork.freedesktop.org/series/85082/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15873 -> Patchwork_85082v3
Summary
---
**
== Series Details ==
Series: drm/i915/dp: 128b/132b uncompressed SST (rev2)
URL : https://patchwork.freedesktop.org/series/142547/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dp: 128b/132b uncompressed SST (rev2)
URL : https://patchwork.freedesktop.org/series/142547/
State : warning
== Summary ==
Error: dim checkpatch failed
90b7afc2e7f6 drm/mst: remove mgr parameter and debug logging from
drm_dp_get_vc_payload_bw()
ed57d41e01
On 12/19/2024 1:00 PM, Rodrigo Vivi wrote:
sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.
LGTM,
Reviewed-by: Vinay Belgaumkar
VLK: 16314, 4304
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/133
If we look at how the members of struct intel_global_state_funcs, we see
a common pattern repeating itself. We can reduce such boilerplate by
moving the common implementation to the generic global state code. This
series proposes that.
Gustavo Sousa (3):
drm/i915/display: Do not assume zero offs
If we look at how the members of struct intel_global_state_funcs, we see
a common pattern repeating itself. Let's add the necessary
infra-structure to allow reducing the boilerplate. We do that by
adding common generic implementations for each member and adding a macro
INTEL_GLOBAL_STATE_DEFAULTS()
Reduce global state boilerplate by using INTEL_GLOBAL_STATE_DEFAULTS().
The only case that requires customization is for the duplication of
CDCLK state, which is resolved by wrapping the generic implementation.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_bw.c | 21 +
The current intel_*_duplicate_state() functions assume the offset for
the base member of their state structures is zero when calling
kmemdup(). While that is true today, such assumption should not be made
and proper offset must be applied when calling kmemdup(), otherwise we
will be duplicating the
Write the payload allocation table for 128b/132b SST. Use VCPID 1 and
start from slot 0, with dp_m_n.tu slots.
This is preparation for enabling 128b/132b SST. This path is not
reachable yet. Indeed, we don't yet compute TU for 128b/132b SST.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/d
128b/132b SST needs 128b/132b mode enabled in the TRANS_DDI_FUNC_CTL
register.
This is preparation for enabling 128b/132b SST. This path is not
reachable yet.
v2: Use the MST path instead of SST to also set transport select (Imre)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/int
The crtc_state->pbn member is only used as a temporary variable within
mst_stream_find_vcpi_slots_for_bpp(). Remove it as unnecessary.
Suggested-by: Imre Deak
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_types.h | 2 --
drivers/gpu/drm/i915/display/intel_dp_mst.c
Add ACT handling for 128b/132b SST.
This is preparation for enabling 128b/132b SST. This path is not
reachable yet.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
Enable basic 128b/132b SST functionality without compression. Reuse
intel_dp_mtp_tu_compute_config() to figure out the TU after we've
determined we need to use an UHBR rate.
It's slightly complicated as the M/N computation is done in different
places in MST and SST paths, so we need to avoid trash
We'll want to distinguish 128b/132b SST and MST modes at state
readout. There's a catch, though. From the hardware perspective,
128b/132b SST and MST programming are pretty much the same. And we can't
really ask the sink at this point.
If we have more than one transcoder in 128b/132b mode associat
128b/1232b SST will have mst_master_transcoder set and matching
cpu_transcoder. Ensure disable also for 128b/132b SST.
Co-developed-by: Imre Deak
Signed-off-by: Imre Deak
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deleti
We'll only ever get here in MST mode from MST stream encoders; the
primary encoder's ->get_config() won't be called when we've detected
it's MST.
v2: Read mst_master_transcoder in 128b/132b SST path (Imre)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 19
Write the DP2 specific VFREQ registers.
This is preparation for enabling 128b/132b SST. This path is not
reachable yet.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dd
It's not very clearly specified, and the hardware bit is ill-named, but
128b/132b SST also needs the MST mode set in the DP_TP_CTL register.
This is preparation for enabling 128b/132b SST. This path is not
reachable yet.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c |
Extract intel_dp_mtp_tu_compute_config() for figuring out the TU. Move
the link configuration and mst state access to the callers. This will be
easier to adapt to 128b/132b SST.
v2: Don't add SST stuff here yet
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 53
Handle 128b/132b SST in intel_dp_mtp_tu_compute_config(). The remote
bandwidth overhead and time slot allocation are only relevant for MST;
SST only needs the local bandwidth and a check that 64 slots isn't
exceeded.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10
The callers of mst_stream_find_vcpi_slots_for_bpp() don't need the
returned slots for anything. On the contrary, they need to jump through
hoops to just distinguish between success and failure. Just return 0
instead of slots from mst_stream_find_vcpi_slots_for_bpp() for success,
and simplify the ca
This is v2 of [1], enabling uncompressed 128b/132b UHBR SST.
The first one was accidentally "RFC v0", and there have been a few
iterations sent to CI trybot since, with various version numbers, so I
expect everyone to get royally confused about the versioning
here. Sorry.
Anyway, unlike with [1],
intel_dp_mst_compute_m_n() doesn't need the connector. Remove the
parameter.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/displa
intel_dp_mst_bw_overhead() doesn't need the connector. Remove the
parameter.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/dis
The struct drm_dp_mst_topology_mgr *mgr parameter is only used for debug
logging in case the passed in link rate or lane count are zero. There's
no further error checking as such, and the function returns 0.
There should be no case where the parameters are zero. The returned
value is generally use
-Original Message-
> From: Roper, Matthew D
> Sent: Thursday, December 19, 2024 12:50 PM
> To: Cavitt, Jonathan
> Cc: Vodapalli, Ravi Kumar ;
> intel-gfx@lists.freedesktop.org; Vivekanandan, Balasubramani
> ; De Marchi, Lucas
> ; Sousa, Gustavo ; Taylor,
> Clinton A ; Atwood, Matthew
sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.
VLK: 16314, 4304
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381
Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.")
Cc: Vinay Belgaum
On Thu, Dec 19, 2024 at 11:39:07AM -0800, Cavitt, Jonathan wrote:
> -Original Message-
> From: Intel-gfx On Behalf Of Ravi
> Kumar Vodapalli
> Sent: Thursday, December 19, 2024 9:37 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Vivekanandan, Balasubramani ;
> Roper, Matthew D ; De March
Quoting Cavitt, Jonathan (2024-12-19 16:39:07-03:00)
>-Original Message-
>From: Intel-gfx On Behalf Of Ravi
>Kumar Vodapalli
>Sent: Thursday, December 19, 2024 9:37 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivekanandan, Balasubramani ; Roper,
>Matthew D ; De Marchi, Lucas
>; Sousa,
-Original Message-
From: Intel-gfx On Behalf Of Ravi
Kumar Vodapalli
Sent: Thursday, December 19, 2024 9:37 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vivekanandan, Balasubramani ; Roper,
Matthew D ; De Marchi, Lucas
; Sousa, Gustavo ; Taylor,
Clinton A ; Atwood, Matthew S
; Bhadane,
Hi Sebastian,
On Thu, Dec 19, 2024 at 03:31:52PM +, Sebastian Brzezinka wrote:
> TAINT_WARN is used to notify CI about non-recoverable failures, which
> require device to be restarted. In some cases, there is no sufficient
> information about the reason for the restart. The test runner is just
== Series Details ==
Series: drm/i915/display: Don't program DBUF_CTL tracker state service (rev2)
URL : https://patchwork.freedesktop.org/series/142744/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15873 -> Patchwork_142744v2
=
Hi Dave, Simona,
(Second?) last pull request for the year. Happy holidays!
Cheers,
~Maarten
drm-misc-fixes-2024-12-19:
drm-misc-fixes for v6.13-rc4:
- udma-buf fixes related to sealing.
- dma-buf build warning fix when debugfs is not enabled.
- Assorted drm/panel fixes.
- Correct error return i
While display initialization along with MBUS credits programming
DBUF_CTL register is also programmed, as a part of it the tracker
state service field is also set to 0x8 value when default value is
other than 0x8 which are for platforms past display version 13.
For remaining platforms the default v
-Original Message-
From: Bhadane, Dnyaneshwar
Sent: Thursday, December 19, 2024 12:55 PM
To: Vodapalli, Ravi Kumar ;
intel-gfx@lists.freedesktop.org
Cc: Vivekanandan, Balasubramani ; Roper,
Matthew D ; De Marchi, Lucas
; Sousa, Gustavo ; Taylor,
Clinton A ; Atwood, Matthew S
; Kalv
== Series Details ==
Series: annotate i915_gem_object_trylock() as __must_check
URL : https://patchwork.freedesktop.org/series/142836/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15873 -> Patchwork_142836v1
Summary
--
== Series Details ==
Series: annotate i915_gem_object_trylock() as __must_check
URL : https://patchwork.freedesktop.org/series/142836/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: annotate i915_gem_object_trylock() as __must_check
URL : https://patchwork.freedesktop.org/series/142836/
State : warning
== Summary ==
Error: dim checkpatch failed
d9ac0678af4a drm/i915/selftests: check the return value of
i915_gem_object_trylock()
72b7193baf3f d
== Series Details ==
Series: Remove get_task_comm() and print task comm directly
URL : https://patchwork.freedesktop.org/series/142837/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/142837/revisions/1/mbox/ not
applied
Applying: kernel: Remove ge
When you don't look at the return code you can't know if you actually got the
lock.
Signed-off-by: Rolf Eike Beer
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i
Since task->comm is guaranteed to be NUL-terminated, we can print it
directly without the need to copy it into a separate buffer. This
simplifies the code and avoids unnecessary operations.
Signed-off-by: Yafang Shao
Cc: Vineet Gupta
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: Borislav Petkov
Cc:
Since task->comm is guaranteed to be NUL-terminated, we can print it
directly without the need to copy it into a separate buffer. This
simplifies the code and avoids unnecessary operations.
Signed-off-by: Yafang Shao
Cc: Johannes Berg
---
net/wireless/wext-core.c | 4 +---
1 file changed, 1 ins
Since task->comm is guaranteed to be NUL-terminated, we can print it
directly without the need to copy it into a separate buffer. This
simplifies the code and avoids unnecessary operations.
Signed-off-by: Yafang Shao
Reviewed-by: Paul Moore
Acked-by: Kees Cook
Cc: James Morris
Cc: "Serge E. Ha
Since task->comm is guaranteed to be NUL-terminated, we can print it
directly without the need to copy it into a separate buffer. This
simplifies the code and avoids unnecessary operations.
Signed-off-by: Yafang Shao
Cc: Serge Hallyn
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: Peter Zijlstra
Cc:
A trylock can fail, in which case operating on the object is unsafe and
unconditionally unlocking is wrong.
Signed-off-by: Rolf Eike Beer
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrat
Since task->comm is guaranteed to be NUL-terminated, we can print it
directly without the need to copy it into a separate buffer. This
simplifies the code and avoids unnecessary operations.
Signed-off-by: Yafang Shao
Reviewed-by: Jiri Slaby (For tty)
Reviewed-by: Lyude Paul (For nouveau)
Cc: Od
A while ago I did an attempt to convert some *_trylock*() functions to
__must_check annotation. I have refreshed that and the only new compile error
I found was in i915/gt/selftest_migrate.c.
Here is what I have come up with as a solution for this. I have not observed
any actual error about thi
Since task->comm is guaranteed to be NUL-terminated, we can print it
directly without the need to copy it into a separate buffer. This
simplifies the code and avoids unnecessary operations.
v1->v2:
- Don't add "%pTN" (Petr, Kalle, Borislav, Andy, Linus)
v1: https://lore.kernel.org/all/20241213054
On Thu, Dec 12, 2024 at 08:03:28PM +0530, Nemesa Garg wrote:
> In panel fitter/pipe scaler scenario the pch_pfit configuration
> currently takes place before accounting for pipe_src width for
> joiner. This causes issue when pch_pfit and joiner get enabled
> together.So once pipe src is computed ad
> -Original Message-
> From: Cavitt, Jonathan
> Sent: Thursday, December 12, 2024 9:25 PM
> To: Garg, Nemesa ; intel-gfx@lists.freedesktop.org;
> intel...@lists.freedesktop.org
> Cc: Garg, Nemesa ; Cavitt, Jonathan
>
> Subject: RE: [PATCH 2/2] drm/i915/display: Initialize pipe_src in c
> -Original Message-
> From: Cavitt, Jonathan
> Sent: Thursday, December 12, 2024 9:24 PM
> To: Garg, Nemesa ; intel-gfx@lists.freedesktop.org;
> intel...@lists.freedesktop.org
> Cc: Garg, Nemesa ; Cavitt, Jonathan
>
> Subject: RE: [PATCH 1/2] drm/i915/display: After joiner compute pfit
== Series Details ==
Series: drm/i915/scaler: Scaler cleanups and tracepoints
URL : https://patchwork.freedesktop.org/series/142828/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15871 -> Patchwork_142828v1
Summary
---
== Series Details ==
Series: drm/i915/scaler: Scaler cleanups and tracepoints
URL : https://patchwork.freedesktop.org/series/142828/
State : warning
== Summary ==
Error: dim checkpatch failed
5e3d242efe8e drm/i915/scaler: Extract skl_scaler_min_src_size()
32e8df2e586f drm/i915/scaler: Extract
On Thu, Dec 19, 2024 at 01:35:11PM +0200, Jani Nikula wrote:
> On Thu, 19 Dec 2024, "Kahola, Mika" wrote:
> > Thanks for the review! Patch is now merged with the change of naming
> > to XE3_*. This is used elsewhere in the driver so maybe it's ok to use
> > here as well.
>
> Nag, I don't really l
From: Ville Syrjälä
Add some tracpoints around skl+ scaler programming to help with
debugging.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_trace.h| 99 +++
drivers/gpu/drm/i915/display/skl_scaler.c | 8 ++
2 files changed, 107 insertions(+)
dif
From: Ville Syrjälä
Fix typo s/excdeed/exceed/
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
b/drivers/gpu/drm/i915/display/skl_scaler.c
index f6d76ef1a85
From: Ville Syrjälä
Include the standard "[CRTC:...]" information in the scaler debugs
to make life easier.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 25 +++
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i9
From: Ville Syrjälä
The tgl+ and mtl+ numbers in skl_scaler_max_dst_size() are
identical. Combine them to a single piece of code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i
From: Ville Syrjälä
The SKL_MAX_DST_* defines just make things hard to read.
Get rid of them and introduce an easy to read function
in their place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 44 +++
1 file changed, 21 insertions(+), 23 dele
From: Ville Syrjälä
The SKL_MAX_SRC_* defines just make things hard to read.
Get rid of them and introduce an easy to read function
in their place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 37 +--
1 file changed, 21 insertions(+), 16 dele
From: Ville Syrjälä
The SKL_MIN_DST_* defines just make things hard to read.
Get rid of them and introduce an easy to read function
in their place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff
From: Ville Syrjälä
The SKL_MIN_*SRC_* defines just make things hard to read.
Get rid of them and introduce an easy to read function
in their place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_scaler.c | 25 ---
1 file changed, 13 insertions(+), 12 del
From: Ville Syrjälä
Do a bunch of cleanup in the scaler code, and add rudimentary
scaler tracpoints to aid debugging.
Ville Syrjälä (8):
drm/i915/scaler: Extract skl_scaler_min_src_size()
drm/i915/scaler: Extract skl_scaler_max_src_size()
drm/i915/scaler: Extract skl_scaler_min_dst_size()
Hi Dave, Sima,
Here's this week drm-misc-next PR.
Maxime
drm-misc-next-2024-12-19:
drm-misc-next for 6.14:
UAPI Changes:
Cross-subsystem Changes:
Core Changes:
- connector: Add a mutex to protect ELD access, Add a helper to create
a connector in two steps
Driver Changes:
- amdxdna: A
On Thu, 19 Dec 2024, "Kahola, Mika" wrote:
> Thanks for the review! Patch is now merged with the change of naming
> to XE3_*. This is used elsewhere in the driver so maybe it's ok to use
> here as well.
Nag, I don't really like modifying patches while applying. Personally, I
try to avoid it altog
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, 18 December 2024 16.57
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: Re: [PATCH v2] drm/i915/display: UHBR rates for Thunderbolt
>
> On Tue, Dec 17, 2024 at 04:34:40PM +0200,
Hi Sk,
On Fri, Nov 29, 2024 at 09:17:16PM +0530, Sk Anirban wrote:
> Add RC6 & RC0 frequency printing to ensure accurate energy
> readings aimed at addressing GPU energy leaks and power
> measurement failures.
> Also update sleep time for RC6 mode to match RC0.
>
> v2:
> - Improved commit messa
> > +
> > +static ssize_t idg_nvm_rewrite_partial(struct intel_dg_nvm *nvm, loff_t to,
> > + loff_t offset, size_t len, const u32
> *newdata)
> > +{
> > + u32 data = idg_nvm_read32(nvm, to);
> > +
> > + if (idg_nvm_error(nvm))
> > + return -EIO;
> > +
Hi Sk,
On Fri, Nov 29, 2024 at 09:17:16PM +0530, Sk Anirban wrote:
> Add RC6 & RC0 frequency printing to ensure accurate energy
> readings aimed at addressing GPU energy leaks and power
> measurement failures.
> Also update sleep time for RC6 mode to match RC0.
>
> v2:
> - Improved commit messa
Hi Nitin,
On Tue, Dec 17, 2024 at 12:05:32PM +0530, Nitin Gote wrote:
> Issue seen again where engine resets fails because the engine resumes from
> an incorrect RING_HEAD. HEAD is still not 0 even after writing into it.
> This seems to be timing issue and we experimented different values from 5ms
Hi Sebastian,
On Wed, Dec 18, 2024 at 07:55:30PM +, Sebastian Brzezinka wrote:
> Adding TAINT_WARN is expected when GPU cannot be restarted, informing
> about it will make it easier to find the source of the failure.
>
> Right now TAINT_WARN will cause CI machine to restart, leaving only err
== Series Details ==
Series: drm/i915/gvt: store virtual_dp_monitor_edid in rodata (rev2)
URL : https://patchwork.freedesktop.org/series/142793/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15868 -> Patchwork_142793v2
Summ
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