== Series Details ==
Series: drm/i915/display: UHBR rates for Thunderbolt
URL : https://patchwork.freedesktop.org/series/142727/
State : warning
== Summary ==
Error: dim checkpatch failed
19bc4c36b471 drm/i915/display: UHBR rates for Thunderbolt
-:87: WARNING:LONG_LINE: line length of 106 exce
== Series Details ==
Series: drm/i915/display: drop unnecessary i915_drv.h includes (rev2)
URL : https://patchwork.freedesktop.org/series/142669/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15861 -> Patchwork_142669v2
Sum
> >> @@ -474,20 +478,28 @@ static int intel_dg_mtd_erase(struct mtd_info
> *mtd, struct erase_info *info)
> >>total_len = info->len;
> >>addr = info->addr;
> >>
> >> + ret = pm_runtime_resume_and_get(mtd->dev.parent);
> > on this, I really don't believe this is right and we should use
> >
On 18-12-2024 04:19, Rodrigo Vivi wrote:
On Tue, Nov 19, 2024 at 04:01:08PM +0200, Alexander Usyskin wrote:
Enable runtime PM in mtd driver to notify graphics driver that
whole card should be kept awake while nvm operations are
performed through this driver.
CC: Lucas De Marchi
Acked-by: Miq
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Tuesday, December 17, 2024 3:03 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Kandpal, Suraj ;
> jani.nik...@linux.intel.com; Deak, Imre
> Subject: [PATCH 14/14] drm/i915/dp_mst: Use link.{min/max}_
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Tuesday, December 17, 2024 3:03 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Kandpal, Suraj ;
> jani.nik...@linux.intel.com; Deak, Imre
> Subject: [PATCH 10/14] drm/i915/dp_mst: Use pipe_bpp-
> >li
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Tuesday, December 17, 2024 6:52 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [PATCH v2] drm/i915/display: drop unnecessary i915_drv.h includes
>
> Now tha
[Thanks, Imre for the heads up and help with the conflict resolution]
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/display/intel_dp_mst.c
between commit:
6fe7b1d10cbd ("drm/i915/dp_mst: Expose a connector to kernel users after it's
properl
On Tue, Nov 19, 2024 at 04:01:08PM +0200, Alexander Usyskin wrote:
> Enable runtime PM in mtd driver to notify graphics driver that
> whole card should be kept awake while nvm operations are
> performed through this driver.
>
> CC: Lucas De Marchi
> Acked-by: Miquel Raynal
> Signed-off-by: Alexa
On Tue, Nov 19, 2024 at 04:01:05PM +0200, Alexander Usyskin wrote:
> Implement read(), erase() and write() functions.
>
> CC: Lucas De Marchi
> CC: Rodrigo Vivi
> Acked-by: Miquel Raynal
> Co-developed-by: Tomas Winkler
> Signed-off-by: Tomas Winkler
> Co-developed-by: Vitaly Lubart
> Signed
> -Original Message-
> From: Vodapalli, Ravi Kumar
> Sent: Tuesday, December 17, 2024 11:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Vivekanandan, Balasubramani
> ; Roper, Matthew D
> ; De Marchi, Lucas
> ; Sousa, Gustavo ;
> Taylor, Clinton A ; Atwood, Matthew S
> ; Bhadane, Dnya
In the C20 algorithm for HDMI TMDS, certain fields have been
updated as per the specs for Xe2LPG, Xe2HPD and MTL/ARL platforms
and subplatforms.This series update fields that need to be set
based on the platforms/subplatforms types. Also added definition
for MTL-u subplatforms.
Dnyaneshwar Bhadane
In the C20 algorithm for HDMI TMDS, certain fields have been updated
in the BSpec to set values for SRAM_GENERIC__TX_CNTX_CFG_1,
such as tx_misc and dac_ctrl_range for Xe2LPD, Xe2HPD and MTL/ARL.
This patch covers fields that need to be set based on the platform type.
Some ARLs SoCs cannot be dire
Separate MTL-U platform PCI ids in one define macro.
Add the MTL U/ARL U as subplatform member in MTL platform description
structure to use display.platform. from intel_display
structure instead of IS_() in display code path.
v2:
- Club ARL-u in MTL and identify ARL-u as MTL-u subplatform(Jani)
On Tue, Nov 19, 2024 at 04:01:04PM +0200, Alexander Usyskin wrote:
> In intel-dg, there is no access to the spi controller,
> the information is extracted from the descriptor region.
>
> CC: Rodrigo Vivi
> CC: Lucas De Marchi
> Acked-by: Miquel Raynal
> Co-developed-by: Tomas Winkler
> Signed-
On Mon, Dec 16, 2024 at 04:57:04PM -0800, Vinay Belgaumkar wrote:
> Default SLPC power profile is Base(0). Power Saving mode(1)
> has conservative up/down thresholds and is suitable for use with
> apps that typically need to be power efficient.
>
> Cc: Sushma Venkatesh Reddy
> Cc: Rodrigo Vivi
>
Let's peak on the Balancer and DCC status, now that we
are using the default strategies.
v2: fix identation
Cc: Vinay Belgaumkar
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i9
Check if dsc prefill latency is sufficient for vblank.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/skl_watermark.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark
Add scaling factors to scaler_state for a perticular scaler user,
use it later to compute scaler prefill latency. Also to extend this
when either pipe or plane scaler is in use.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++
drivers/gpu/drm/i915/displa
Check if vblank is too short for scaler and dsc prefill latency.
Reference: https://patchwork.freedesktop.org/series/141203/
Mitul Golani (6):
drm/i915/scaler: Add and compute scaling factors
drm/i915/scaler: Add member to track scaler user
drm/i915/scaler: Use crtc_state to setup plane or
Parse crtc_state to intel_atomic_setup_scaler, this will help to
check if pch_pfit enabled or not and also will be useful to parse
scaler_state with the same.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/skl_scaler.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
Add enum to track scaler user, this differenciates between
the current user of scaler, either plane scaler/pipe scaler or
in case no scaler is used.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display_types.h | 7 +++
drivers/gpu/drm/i915/display/skl_scaler.c
Compute scaling factors and scaler user for pipe scaler if
perticular scaler user is pipe scaler.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/skl_scaler.c | 37 ---
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/sk
Check if vblank is too short for scaler prefill latency.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/skl_watermark.c | 22
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_waterma
Hi Andi,
On Tuesday, 17 December 2024 18:12:08 CET Andi Shyti wrote:
> Hi Janusz,
>
> ...
>
> > > > +
> > > > cond_resched();
> > > >
> > > > - if (intel_gt_wait_for_idle(gt, HZ * 3) == -ETIME) {
> > > > + if (intel_gt_wait_for_idle(gt, HZ * timeout_
Hi Nitin,
...
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 32f3b52a183a..d56410863f26 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -230,8 +
Hi Nitin,
On Tue, Dec 17, 2024 at 03:30:58PM +0530, Nitin Gote wrote:
> Instead of drm_err(), prefer gt_err() and ENGINE_TRACE()
> for GEM tracing in i915. So, it will be good to use ENGINE_TRACE()
> over drm_err() drm_device based logging for engine debug log.
>
> v2: Bit more specific in commit
While display initialization along with MBUS credits programming
DBUF_CTL register is also programmed, as a part of it the tracker
state service field is also set to 0x8 value when default value is
other than 0x8 which are for platforms past display version 13.
For remaining platforms the default v
Hi Janusz,
...
> > > +
> > > cond_resched();
> > >
> > > - if (intel_gt_wait_for_idle(gt, HZ * 3) == -ETIME) {
> > > + if (intel_gt_wait_for_idle(gt, HZ * timeout_ms / 500) == -
> ETIME) {
> >
> > where is this 500 coming from?
>
> / 1000 would convert it to seconds
Uprev IGT to the latest version and update expectation files.
Signed-off-by: Vignesh Raman
---
v1:
- Pipeline link -
https://gitlab.freedesktop.org/vigneshraman/linux/-/pipelines/1327810
Will update the flake bug report link after v1 is reviewed.
v2:
- Pipeline link -
https://gitlab.f
On Thu, Dec 12, 2024 at 01:03:17AM +0200, Imre Deak wrote:
The patchset at [2] is pushed now to drm-misc-next, thanks for the
reviews, acks and ideas.
While merging, I fixed the typos in patch 3, 5-7 and removed references
to 'patches', 'patchsets' in the commit logs of patch 2, 4, 9.
I had to r
tbt-alt mode is missing uhbr rates 10G and 20G. This requires
requires pll clock rates 312.5 MHz and 625 MHz to be added,
respectively. The uhbr rates are supported only form PTL+
platforms.
v2: Add drm_WARN_ON() to check if port clock is not supported by
the platform (Imre)
Combine forwar
There's something funky going on here, please look into it.
On Fri, 13 Dec 2024, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display: handle hdmi connector init failures, and no HDMI/DP
> cases (rev2)
> URL : https://patchwork.freedesktop.org/series/142119/
> State : failure
Now that we don't include i915_drv.h via any headers from display, we
can reliably remove unnecessary i915_drv.h includes and be sure they're
not indirectly included. Add other includes where needed.
v2: Fix 32-bit build
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/dvo_ns2501.c
On 12/16/2024 11:45 PM, Suraj Kandpal wrote:
According to spec VDR_CUSTOM_WIDTH register gets programmed after pll
specific VDR registers and TX Lane programming registers are done.
Moreover we only program into C10_VDR_CONTROL1 to update config and
setup master lane once all VDR registers are
== Series Details ==
Series: drm/i915/gt: Use ENGINE_TRACE for tracing. (rev5)
URL : https://patchwork.freedesktop.org/series/140358/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15858 -> Patchwork_140358v5
Summary
---
== Series Details ==
Series: DP DSC min/max src bpc fixes (rev11)
URL : https://patchwork.freedesktop.org/series/125571/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15858 -> Patchwork_125571v11
Summary
---
**SUCCES
== Series Details ==
Series: DP DSC min/max src bpc fixes (rev11)
URL : https://patchwork.freedesktop.org/series/125571/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1
== Series Details ==
Series: drm/i915/xe3: FBC Dirty rect feature support (rev2)
URL : https://patchwork.freedesktop.org/series/141527/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15858 -> Patchwork_141527v2
Summary
-
== Series Details ==
Series: drm/i915/xe3: FBC Dirty rect feature support (rev2)
URL : https://patchwork.freedesktop.org/series/141527/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/xe3: FBC Dirty rect feature support (rev2)
URL : https://patchwork.freedesktop.org/series/141527/
State : warning
== Summary ==
Error: dim checkpatch failed
016053a17deb drm/i915/xe: add register definitions for fbc dirty rect support
-:24: WARNING:LONG_LI
Em 17/12/2024 05:42, Raag Jadav escreveu:
On Thu, Dec 12, 2024 at 03:50:29PM -0300, André Almeida wrote:
Em 28/11/2024 12:37, Raag Jadav escreveu:
Add documentation for device wedged event in a new 'Device wedging'
chapter. The describes basic definitions, prerequisites and consumer
expectation
On Tue, 17 Dec 2024, Jani Nikula wrote:
> On Tue, 17 Dec 2024, Ankit Nautiyal wrote:
>> Check for DSC support before computing link config with DSC.
>> For DP MST we are already doing the same.
>>
>> Signed-off-by: Ankit Nautiyal
>> Reviewed-by: Suraj Kandpal
>> ---
>> drivers/gpu/drm/i915/dis
On Tue, 17 Dec 2024, Ankit Nautiyal wrote:
> Support for FEC is already checked by intel_dp_supports_dsc() in
> intel_dp_dsc_compute_config() which gets called before
> intel_dp_fec_compute_config().
>
> Therefore the check can be dropped from the helper
> intel_dp_fec_compute_config().
>
> v2: Ch
On Tue, 17 Dec 2024, Ankit Nautiyal wrote:
> Make a separate function for setting fec_enable in crtc_state.
>
> v2: Rename helper to align with encoder->compute_config() callback
> and other minor fixes. (Jani)
>
> Signed-off-by: Ankit Nautiyal
> Reviewed-by: Suraj Kandpal
Reviewed-by: Jani Nik
On Tue, 17 Dec 2024, Ankit Nautiyal wrote:
> Check for DSC support before computing link config with DSC.
> For DP MST we are already doing the same.
>
> Signed-off-by: Ankit Nautiyal
> Reviewed-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
> 1 file changed, 3 in
On Tue, 17 Dec 2024, Ankit Nautiyal wrote:
> Forward Error Correction is required for DP if we are using DSC but
> is optional for eDP.
>
> Currently the helper intel_dp_supports_dsc checks if fec_enable is set for
> DP or not. The helper is called after fec_enable is set in crtc_state.
>
> Instea
== Series Details ==
Series: drm/i915/hdcp: Fix Repeater authentication during topology change
URL : https://patchwork.freedesktop.org/series/142698/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15856 -> Patchwork_142698v1
Am 16.12.24 um 17:21 schrieb André Almeida:
Use DRM's device wedged event to notify userspace that a reset had
happened. For now, only use `none` method meant for telemetry
capture.
In the future we might want to report a recovery method if the reset didn't
succeed.
Acked-by: Shashank Sharma
S
Instead of drm_err(), prefer gt_err() and ENGINE_TRACE()
for GEM tracing in i915. So, it will be good to use ENGINE_TRACE()
over drm_err() drm_device based logging for engine debug log.
v2: Bit more specific in commit description (Andi)
v3: Use gt_err() along with ENGINE_TRACE() in place of drm_e
Currently we are including both max_requested_bpc and
limits->pipe.bpp_max while computing maximum possible pipe bpp with dsc.
However, while setting limits->pipe.max_bpp, the max_requested_bpc is
already taken into account.
Drop the redundant check for max_requested_bpc and use only
limits->pipe.
The dsc limits->pipe.max/min_bpp are already set in
intel_dp_compute_config_limits.
Use the limits while computing the link config with DSC for MST.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff -
The helper intel_dp_compute_config_link_bpp_limits is the correct place
to set the DSC link limits. Move the code to this function and remove
the #TODO item.
v2: Add argument intel_connector to the helper to get correct connector
for DP MST. (Imre)
v3: Remove redundant calls to intel_dp_dsc_sink_
The link.{min/max}_bpp_x16 is already set in crtc_state, use that while
computing link config for MST.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_
Make a separate function for setting fec_enable in crtc_state.
v2: Rename helper to align with encoder->compute_config() callback
and other minor fixes. (Jani)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 ++---
1
Use helpers for source min/max input bpc with DSC.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 13 +
3 files chang
Modify the dsc helpers to get max/min compressed bpp to accept
`const struct intel_crtc_state *` pointers instead of
`struct intel_crtc_state *`.
These helpers are not supposed to modify `crtc_state`.
Accepting const pointers will allow these helpers to be called from
functions that have const poi
Currently to get the max pipe_bpp with dsc we take the min of
limits->pipe.max_bpp and dsc max bpp (dsc max bpc * 3). This can result
in problems when limits->pipe.max_bpp is less than the computed dsc min bpp
(dsc min bpc * 3).
Replace the min/max functions with clamp while computing
limits->pipe
Use ints for dsc_max/min_bpc instead of u8 in
dsc_max/min_src_input_bpc helpers and their callers.
This will also help replace min_t/max_t macros with min/max ones.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
1 fi
With DSC there are additional limits for pipe_bpp. Currently these are
scattered in different places.
Instead set the limits->pipe.max/min_bpp in one place and use them
wherever required.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp.c | 49 +
DSC support is already checked before the helper
intel_dp_dsc_max_src_input_bpc is called.
Remove the check from the helper.
v2: Drop the argument struct drm_i915_private *i915. (Suraj)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 +++
Support for FEC is already checked by intel_dp_supports_dsc() in
intel_dp_dsc_compute_config() which gets called before
intel_dp_fec_compute_config().
Therefore the check can be dropped from the helper
intel_dp_fec_compute_config().
v2: Changed commit message for clarity. (Suraj)
Signed-off-by:
Check for DSC support before computing link config with DSC.
For DP MST we are already doing the same.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i
Use helpers for source min/max src bpc appropriately for dp mst case and
to limit max_requested_bpc property min/max values.
Rev2: Drop patch to limit max_requested_bpc based on src DSC bpc
limits. Instead add change to ignore max_requested_bpc if its
too low for DSC.
Rev3: Update patch#1 commit
Forward Error Correction is required for DP if we are using DSC but
is optional for eDP.
Currently the helper intel_dp_supports_dsc checks if fec_enable is set for
DP or not. The helper is called after fec_enable is set in crtc_state.
Instead of this a better approach would be to:
first, call int
On Fri, 2024-12-13 at 15:00 +0530, Swati Sharma wrote:
> Number of DSC slices can be shown in the DSC debugfs so that
> test can take a call whether the configuration can support forcing
> bigjoiner/ultrajoiner.
>
This is now pushed to drm-intel-next.
BR,
Jouni Högander
> v2: used intel_dp_is_
== Series Details ==
Series: drm/i915/dsc: Expose dsc sink max slice count via debugfs
URL : https://patchwork.freedesktop.org/series/142537/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15837 -> Patchwork_142537v1
Summary
It is not recommended to have both FBC and PSR2 selective fetch
be enabled at the same time in a plane. If PSR2 selective fetch
or panel replay is on, mark FBC as not possible in that plane.
v2: fix the condition to disable FBC if PSR2 enabled (Jani)
Bspec: 68881
Signed-off-by: Vinod Govindapilla
Dirty rect support for FBC in xe3 onwards based on the comments after the
initial RFC series.
v2: Dirty rect related compute and storage moved to fbc state (Ville)
Vinod Govindapillai (3):
drm/i915/xe: add register definitions for fbc dirty rect support
drm/i915/xe3: add dirty rect support fo
Register definitions for FBC dirty rect support
Bspec: 71675, 73424
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc_regs.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
b/drivers/gpu/drm/i915/display/inte
Dirty rectangle feature allows FBC to recompress a subsection
of a frame. When this feature is enabled, display will read
the scan lines between dirty rectangle start line and dirty
rectangle end line in subsequent frames.
v2: Move dirty rect handling to fbc state (Ville)
Bspec: 71675, 73424
Sign
On Thu, Dec 12, 2024 at 03:50:29PM -0300, André Almeida wrote:
> Em 28/11/2024 12:37, Raag Jadav escreveu:
> > Add documentation for device wedged event in a new 'Device wedging'
> > chapter. The describes basic definitions, prerequisites and consumer
> > expectations along with an example.
> >
>
When topology changes before beginning a new HDCP authentication by
sending AKE_init message we need to first authenticate only the
repeater if that fails only then makes sense to enable a new HDCP
authentication. Even though it made sense to not enable HDCP directly
from check_link and schedule it
[Public]
Hi Imre,
Thanks for the patch set!
Patch 1~4 & patch 6 & patch 8 are:
Acked-by: Wayne Lin
> -Original Message-
> From: Imre Deak
> Sent: Monday, December 16, 2024 8:24 PM
> To: Wentland, Harry ; Li, Sun peng (Leo)
> ; Lin, Wayne ; Deucher,
> Alexander
> Cc: intel-gfx@lists.fr
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