On Tue, Dec 10, 2024 at 06:19:00PM -0500, Rodrigo Vivi wrote:
> On Sun, Dec 08, 2024 at 03:17:27PM +, Ed Maste wrote:
> > These two files (i915_live_selftests.h, i915_mock_selftests.h) were
> > introduced in commit 953c7f82eb89 ("drm/i915: Provide a hook for
> > selftests") and are effectively
On Tue, Dec 10, 2024 at 01:52:21PM +0100, Andi Shyti wrote:
> Hi Raag,
>
> > +/* Wa_14022698537:dg2 */
> > +static void i915_enable_g8(struct drm_i915_private *i915)
> > +{
> > + if (IS_DG2(i915)) {
> > + if (IS_DG2_D(i915) && !intel_match_g8_cpu())
> > + return;
> >
Hi Dnyaneshwar,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20241209]
[also build test ERROR on linus/master v6.13-rc2]
[cannot apply to drm-intel/for-linux-next drm-intel/for-linux-next-fixes
drm-tip/drm-tip v6.13-rc2 v6.13-rc1 v6.12]
[If your patch is a
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, December 4, 2024 2:57 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Kandpal, Suraj ;
> jani.nik...@linux.intel.com; Deak, Imre
> Subject: [PATCH 14/14] drm/i915/dp: Set the DSC link limit
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, December 4, 2024 2:56 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Kandpal, Suraj ;
> jani.nik...@linux.intel.com; Deak, Imre
> Subject: [PATCH 01/14] drm/i915/dp: Refactor FEC support c
+Peter and Thomas, for question below about the use of raw_spinlock_t in perf
[ Note that the patch by itself is not proposing this revert to be merged in
any tree going to Linus - that would just shoot the messenger - it's
just a temporary stop gap to get our CI running again. Below I'm
lo
== Series Details ==
Series: drm/i915: DSB+VRR
URL : https://patchwork.freedesktop.org/series/142375/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15816_full -> Patchwork_142375v1_full
Summary
---
**FAILURE**
Ser
On Sun, Dec 08, 2024 at 03:17:27PM +, Ed Maste wrote:
> These two files (i915_live_selftests.h, i915_mock_selftests.h) were
> introduced in commit 953c7f82eb89 ("drm/i915: Provide a hook for
> selftests") and are effectively just a list of selftests.
>
> The selftest implementation itself is l
On Tue, Dec 10, 2024 at 09:00:13AM -0800, Lucas De Marchi wrote:
> On Mon, Dec 09, 2024 at 03:53:51PM +0200, Luca Coelho wrote:
> > This reverts commit 560af5dc839eef08a273908f390cfefefb82aa04.
> >
> > Signed-off-by: Luca Coelho
> > ---
> >
> > It seems that we have a few issues with this config
On Tue, Dec 10, 2024 at 10:53:10AM +0200, Raag Jadav wrote:
> On Mon, Dec 09, 2024 at 11:28:39AM -0500, Rodrigo Vivi wrote:
> > On Sat, Dec 07, 2024 at 08:14:42AM +0200, Raag Jadav wrote:
> > > Cc: Chris
> > >
> > > On Fri, Dec 06, 2024 at 10:45:18AM -0500, Rodrigo Vivi wrote:
> > > > On Thu, Dec
== Series Details ==
Series: drm/i915: DSB+VRR
URL : https://patchwork.freedesktop.org/series/142375/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15816 -> Patchwork_142375v1
Summary
---
**SUCCESS**
No regression
== Series Details ==
Series: drm/i915: DSB+VRR
URL : https://patchwork.freedesktop.org/series/142375/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplac
== Series Details ==
Series: drm/i915: DSB+VRR
URL : https://patchwork.freedesktop.org/series/142375/
State : warning
== Summary ==
Error: dim checkpatch failed
8e301254a329 drm/i915: Extract intel_crtc_vblank_delay()
0deffa62d526 drm/i915: Check vblank delay validity
719433263773 drm/i915: Fi
On Fri, Dec 06, 2024 at 11:43:07AM +0200, Dmitry Baryshkov wrote:
> Reading access to connector->eld can happen at the same time the
> drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
> order to protect connector->eld from concurrent access.
>
> Reviewed-by: Maxime Ripard
> S
From: Ville Syrjälä
Turns out that TGL needs its vmin/vmax/flipling adjusted based
on the vblank delay, otherwise the hardware pushes the vtotals
fiurther out. Make it so.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vrr.c | 32 +++-
1 file changed, 2
From: Ville Syrjälä
When looking at raw hardware scanline numbers it's helpful to
remember what the offset between the hardware values and our
more human readable numbers should be. Include that in the state dump.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc_state_d
From: Ville Syrjälä
On ICL/TGL the VRR hardware injects an extra scanline just after
vactive. This essentically behaves the same as an extra line of
vblank delay, except it only appears in this one specific spot.
Considee our DSB interrupt signalling scheme:
1. arm the update
2. wait for undelay
From: Ville Syrjälä
Plumb the DSB down into intel_vrr_send_push() so that we can
perform the opration on the DSB.
TRANS_PUSH, being a transcoder register, needs non-posted writes
to make it through.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
drivers/gp
From: Ville Syrjälä
Apparently on ICL/TGL need the annoying vmin adjustemnt. On
ADL+ we can program flipling==vmin and the hardware actually
respects that properly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vrr.c | 39
1 file changed, 27 inser
From: Ville Syrjälä
We have at least two options for how to do the
TRANS_PUSH_SEND + commit completion signalling
with the DSB:
Option A)
1. trigger TRANS_PUSH_SEND
2. wait for "safe window"
3. signal the interrupt
In this cases step 2 should not do anything if we were already
between vmin a
From: Ville Syrjälä
Introduce a VRR specific function for determining the current
vblank delay. Currently thus will give the same answer as
intel_mode_vblank_delay() but that will change later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c| 18 ++
From: Ville Syrjälä
Now that we know how to issue the push with the DSB we can
allow the DSB to drive the commits even when VRR is active.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/displ
From: Ville Syrjälä
We have approximately two copies of pre_commit_crtc_state(),
one in the DSB code, the other in the vblank evasion code.
Combine them into one. The slight difference between the two
is that vblank evasion doesn't have a full atomic state (when
called from the legacy cursor code
From: Ville Syrjälä
Declutter intel_crtc_update_active_timings() a bit by
moving the code that determines the timings into a separate
function.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletion
From: Ville Syrjälä
Dump the calculated vmin/vmax vtotal values in addition to the
raw vmin/vmax/flipline values. Makes it much easier to see what
kind of scanline values we should be expecting from the hardware.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_crtc_state_dump.c
From: Ville Syrjälä
Extract the code that computes the hardware centric view
of the vblank delay into a helper. We;ll need a slightly
different variant for VRR soon.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c| 3 +--
drivers/gpu/drm/i915/display/intel_vblank.
From: Ville Syrjälä
On ICL/TGL vmin/vmax/flipline won't actually match the
vtotal valeues (currently they do, but that is wrong and
needs to be fixed). Add a few helpers that will compute the
actual vtotal values for us.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c
From: Ville Syrjälä
Pull the vblank delay computation into a separate function.
We'll need more logic here soon and we don't want to pollute
intel_crtc_compute_config() with low level details.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 24 +++---
From: Ville Syrjälä
While one can look at the crtc timings to determine the actual
vblank dealy, it seems nicer to provide a more human readable
dump of it to ease our lives.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 +++-
1 file changed, 3 inser
From: Ville Syrjälä
bunch of DSB and VRR Stuff:
- enable DSB based commits when VRR is active
- fix TGL delayed vblank handling with VRR
- some tweaks to VRR programming for ADL+
- bunch of state dump improvements/etc.
Ville Syrjälä (18):
drm/i915: Extract intel_crtc_vblank_delay()
drm/i915:
From: Ville Syrjälä
Try to dump all the important stuff relating to the display timings
in one spot.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/inte
From: Ville Syrjälä
Include the headers in the correct alphabetical order.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/inte
From: Ville Syrjälä
Make sure we have enough vblank for the computed vblank delay.
Supposedly we'd reject things anyway later if this gets violated,
but it seems niver to do some basic sanity checks early just
so we can't be sure the basic relationship vblank_end > vblank_start
always holds.
Sig
When memory stats is generated fresh everytime by going though all the
BOs, their active information is quite easy to get. But if the stats are
tracked with BO's state this becomes harder since the job scheduling
part doesn't really deal with individual buffers.
Make drm-active- optional to enable
> On Tue, Dec 10, 2024 at 08:42:36AM +, Murthy, Arun R wrote:
> > > On Mon, Dec 09, 2024 at 09:54:55PM +0530, Arun R Murthy wrote:
> > > > Add variables for histogram drm_property, its corrsponding
> > > > crtc_state variables and define the structure pointed by the blob
> > > > property.
> >
== Series Details ==
Series: drm/i915/display: clean up DP Adaptive Sync SDP state mismatch logging
(rev2)
URL : https://patchwork.freedesktop.org/series/142154/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15814_full -> Patchwork_142154v2_full
==
== Series Details ==
Series: drm/i915/dp: convert to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/141929/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15814 -> Patchwork_141929v2
Summary
-
== Series Details ==
Series: drm/i915/dp: convert to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/141929/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15814_full -> Patchwork_141929v2_full
Sum
On Mon, Dec 09, 2024 at 03:53:51PM +0200, Luca Coelho wrote:
This reverts commit 560af5dc839eef08a273908f390cfefefb82aa04.
Signed-off-by: Luca Coelho
---
It seems that we have a few issues with this configuration in xe and
in i915. Let's try to revert it to see if the problems we're seeing
go
> -Original Message-
> From: Intel-gfx On Behalf Of Swati
> Sharma
> Sent: Tuesday, December 10, 2024 7:36 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Sharma, Swati2
>
> Subject: [PATCH 1/1] drm/i915/dsc: Expose dsc sink max slice count via
> debugfs
>
> Expose
== Series Details ==
Series: Expose dsc sink max slice count via debugfs
URL : https://patchwork.freedesktop.org/series/142354/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15814 -> Patchwork_142354v1
Summary
---
**
== Series Details ==
Series: Expose dsc sink max slice count via debugfs
URL : https://patchwork.freedesktop.org/series/142354/
State : warning
== Summary ==
Error: dim checkpatch failed
06d13d827dc9 drm/i915/dsc: Expose dsc sink max slice count via debugfs
-:27: WARNING:LONG_LINE: line length
== Series Details ==
Series: drm/i915/display: clean up DP Adaptive Sync SDP state mismatch logging
(rev2)
URL : https://patchwork.freedesktop.org/series/142154/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15814 -> Patchwork_142154v2
On Tue, Dec 10, 2024 at 01:37:11PM +0100, Greg Kroah-Hartman wrote:
> On Tue, Dec 10, 2024 at 02:24:56PM +0200, Jani Nikula wrote:
> > On Tue, 10 Dec 2024, Genes Lists wrote:
> > > On Tue, 2024-12-10 at 10:58 +0200, Jani Nikula wrote:
> > >> On Tue, 10 Dec 2024, Sakari Ailus
> > >> wrote:
> > >>
== Series Details ==
Series: drm/i915: Add drm_panic support (rev3)
URL : https://patchwork.freedesktop.org/series/141935/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15812_full -> Patchwork_141935v3_full
Summary
---
== Series Details ==
Series: drm/i915/dp: convert to struct intel_display (rev2)
URL : https://patchwork.freedesktop.org/series/141929/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm
On Tue, 2024-12-10 at 10:58 +0200, Jani Nikula wrote:
> On Tue, 10 Dec 2024, Sakari Ailus
> wrote:
> > Hi,
> >
> > > ...
> > > FYI 6.12.4 got a crash shortly after booting in dma_alloc_attrs -
> > > maybe
> > > triggered in ipu6_probe. Crash only happened on laptop with ipu6.
> > > All
> > > othe
Expose dsc sink max slice count via i915_dsc_fec_support debugfs.
This debugfs entry is required in cases, where sink doesn't support
minimum of 8 slices in case of ultrajoiner and minimum of 4 slices
in case of big joiner.
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3387
Signed-
Expose dsc sink max slice count via i915_dsc_fec_support debugfs.
This debugfs entry is required in cases, where sink doesn't support
minimum of 8 slices in case of ultrajoiner and minimum of 4 slices
in case of big joiner.
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3387
Test-wi
> -Original Message-
> From: Intel-xe On Behalf Of Arun R
> Murthy
> Sent: Monday, December 9, 2024 9:55 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCHv2 10/10] drm/i915/histogram: Enab
== Series Details ==
Series: drm/i915: Add drm_panic support (rev3)
URL : https://patchwork.freedesktop.org/series/141935/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15812 -> Patchwork_141935v3
Summary
---
**SUCCE
Hi Raag,
> +/* Wa_14022698537:dg2 */
> +static void i915_enable_g8(struct drm_i915_private *i915)
> +{
> + if (IS_DG2(i915)) {
> + if (IS_DG2_D(i915) && !intel_match_g8_cpu())
> + return;
> +
> + snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,
>
> -Original Message-
> From: dri-devel On Behalf Of
> Arun R Murthy
> Sent: Monday, December 9, 2024 9:55 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCHv3 07/10] drm/i915/display: Handl
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: 05 December 2024 15:01
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [PATCH] drm/i915/display: clean up DP Adaptive Sync SDP state
> mismatch logging
>
> Pas
== Series Details ==
Series: drm/i915: Add drm_panic support (rev3)
URL : https://patchwork.freedesktop.org/series/141935/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Tue, Dec 10, 2024 at 02:24:56PM +0200, Jani Nikula wrote:
> On Tue, 10 Dec 2024, Genes Lists wrote:
> > On Tue, 2024-12-10 at 10:58 +0200, Jani Nikula wrote:
> >> On Tue, 10 Dec 2024, Sakari Ailus
> >> wrote:
> >> > Hi,
> >> >
> >> > > ...
> >> > > FYI 6.12.4 got a crash shortly after booting
On Thu, 05 Dec 2024, Andi Shyti wrote:
> Hi Jani,
>
> On Thu, Dec 05, 2024 at 11:49:33AM +0200, Jani Nikula wrote:
>> Add a helper to print a hex dump to a struct drm_printer. There's no
>> fancy formatting stuff, just 16 space-separated bytes per line, with an
>> optional prefix.
>>
>> Signed-of
On Tue, Dec 10, 2024 at 08:42:36AM +, Murthy, Arun R wrote:
> > On Mon, Dec 09, 2024 at 09:54:55PM +0530, Arun R Murthy wrote:
> > > Add variables for histogram drm_property, its corrsponding crtc_state
> > > variables and define the structure pointed by the blob property.
> > >
> > > struct dr
On Tue, 10 Dec 2024, Genes Lists wrote:
> On Tue, 2024-12-10 at 10:58 +0200, Jani Nikula wrote:
>> On Tue, 10 Dec 2024, Sakari Ailus
>> wrote:
>> > Hi,
>> >
>> > > ...
>> > > FYI 6.12.4 got a crash shortly after booting in dma_alloc_attrs -
>> > > maybe
>> > > triggered in ipu6_probe. Crash only
Hi Raag,
On Wed, Oct 30, 2024 at 08:04:15PM +0530, Raag Jadav wrote:
> Refactor DG2 PCI IDs into D, E and M ranges which will be useful for
> segment specific features.
>
> v3: Rework subplatform naming (Jani)
>
> Signed-off-by: Raag Jadav
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Raag,
On Wed, Oct 30, 2024 at 08:04:17PM +0530, Raag Jadav wrote:
> Having similar naming convention in intel-family.h and intel_device_info.h
> results in redefinition of a few platforms. Define CPU IDs in its own file
> to avoid this.
>
> v3: Move file out of gt directory, add kernel doc (Ri
On Tue, Dec 10, 2024 at 01:33:29PM +0530, Riana Tauro wrote:
> On 10/30/2024 8:04 PM, Raag Jadav wrote:
> > G8 power state entry is disabled due to a limitation on DG2, so we
> > enable it from driver with Wa_14022698537. For now we enable it for
> > all DG2 devices with the exception of a few, for
On Wed, 04 Dec 2024, Imre Deak wrote:
> On Mon, Nov 25, 2024 at 05:19:33PM +0200, Jani Nikula wrote:
>> Add a little bit of documentation around DP MST. This is nowhere near
>> complete nor does it have enough detail. But it's better than nothing,
>> and hopefully gives people a basic grasp of wha
Use the contemporary naming convention of struct intel_connector
*connector. Avoid struct drm_connector use altogether. In a few cases
add local struct drm_display_info and struct intel_display pointers to
help move away from struct drm_connector usage.
Signed-off-by: Jani Nikula
---
drivers/gpu
Going forward, struct intel_display is the main device data structure
for display. Switch to it internally in DP code.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 687 +---
1 file changed, 361 insertions(+), 326 deletions(-)
diff --git a/drivers/
Use the contemporary naming convention of struct intel_encoder *encoder.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 -
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/d
Convert the final stragglers to struct intel_display now that we have
platform identification via it too.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
Convert the intel_dp.[ch] external interfaces to struct intel_display.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 6 ++--
.../drm/i915/display/intel_display_driver.c | 9 ++---
drivers/gpu/drm/i915/display/intel_dp.c | 36 +++
drivers
Rebase of [1].
[1] https://lore.kernel.org/r/cover.1732891498.git.jani.nik...@intel.com
Jani Nikula (5):
drm/i915/dp: s/intel_encoder/encoder/
drm/i915/dp: s/intel_connector/connector/
drm/i915/dp: convert to struct intel_display
drm/i915/dp: convert interfaces to struct intel_display
d
The vaddr of the fbdev framebuffer is private to the struct
intel_fbdev, so this function is needed to access it for drm_panic.
Also the struct i915_vma is different between i915 and xe, so it
requires a few functions to access fbdev->vma->iomap.
Signed-off-by: Jocelyn Falempe
---
v2:
* Add int
On Mon, 09 Dec 2024, "Borah, Chaitanya Kumar"
wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Thursday, December 5, 2024 6:07 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani
>> Subject: [PATCH] drm/i915/pps: include panel power cycle de
On Alderlake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements Y-Tiling support, to still be able to draw
the panic screen. The Tile-4 support found in the latest Intel GPU
will come later.
Signed-off-by: Jocelyn Falempe
---
.../gpu/drm/i915/display/in
This adds drm_panic support for a wide range of Intel GPU. I've
tested it only on 2 laptops, Haswell (with 128MB of eDRAM),
Cometlake.
For hardware using DPT, it's not possible to disable tiling, as you
will need to reconfigure the way the GPU is accessing the
framebuffer.
Signed-off-by: Jocelyn F
This is a draft of drm_panic support for i915.
I've tested it on the 3 intel laptops I have at my disposal.
one Haswell with 128MB of eDRAM, one Cometlake and one Alderlake.
I tested panic in both fbdev console and gnome desktop.
Best regards,
v2:
* Add the proper abstractions to build also fo
Prepare the work for drm_panic support. This is used to map the
current framebuffer, so the CPU can overwrite it with the panic
message.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/i915/display/intel_bo.c| 10 +
drivers/gpu/drm/i915/display/intel_bo.h| 2 ++
drivers/gpu/d
drm_panic draws in linear framebuffer, so it's easier to re-use the
current framebuffer, and disable tiling in the panic handler, to show
the panic screen.
Signed-off-by: Jocelyn Falempe
---
.../drm/i915/display/skl_universal_plane.c| 20 +++
1 file changed, 20 insertions(+)
drm_panic draws in linear framebuffer, so it's easier to re-use the
current framebuffer, and disable tiling in the panic handler, to show
the panic screen.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++
.../drm/i915/display/intel_displa
On Mon, 09 Dec 2024, Maarten Lankhorst wrote:
> Instead of 3 different calls, it should be safe to unify to a single
> call now. This makes the init sequence cleaner, and display less
> tangled.
Needs more explanation.
I thought the goal was to *unify* i915 and xe display init/cleanup. This
dive
On Mon, 09 Dec 2024, "Borah, Chaitanya Kumar"
wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Wednesday, December 4, 2024 9:31 PM
>> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
>> Cc: Nikula, Jani ; Paul Menzel
>>
>> Subject:
On Mon, 09 Dec 2024, Dnyaneshwar Bhadane wrote:
> In the C20 algorithm for HDMI TMDS, certain fields have been updated
> in the BSpec to set values for SRAM_GENERIC__TX_CNTX_CFG_1,
> such as tx_misc and dac_ctrl_range for xe2LPD, xe2HPD and MTL/ARL.
> This patch covers fields that need to be set b
On Mon, Dec 09, 2024 at 11:28:39AM -0500, Rodrigo Vivi wrote:
> On Sat, Dec 07, 2024 at 08:14:42AM +0200, Raag Jadav wrote:
> > Cc: Chris
> >
> > On Fri, Dec 06, 2024 at 10:45:18AM -0500, Rodrigo Vivi wrote:
> > > On Thu, Dec 05, 2024 at 01:44:13PM +0530, Raag Jadav wrote:
> > > > Log throttle rea
> On Mon, Dec 09, 2024 at 09:54:54PM +0530, Arun R Murthy wrote:
> > Display histogram is a hardware functionality where a statistics for 'x'
> > number of frames is generated to form a histogram data. This is
> > notified to the user via histogram event. Compositor will then upon
> > sensing the h
> On Mon, Dec 09, 2024 at 09:54:55PM +0530, Arun R Murthy wrote:
> > Add variables for histogram drm_property, its corrsponding crtc_state
> > variables and define the structure pointed by the blob property.
> >
> > struct drm_histogram and drm_iet defined in
> > include/uapi/drm/drm_mode.h
> >
> >
On 10/30/2024 8:04 PM, Raag Jadav wrote:
G8 power state entry is disabled due to a limitation on DG2, so we
enable it from driver with Wa_14022698537. For now we enable it for
all DG2 devices with the exception of a few, for which, we enable
only when paired with whitelisted CPU models. This w
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