== Series Details ==
Series: drm/i915: Use string enable/disable choice helpers
URL : https://patchwork.freedesktop.org/series/140356/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15581 -> Patchwork_140356v1
Summary
--
Check if Odd pixel is required during DSC compute config and update
the crtc_state to track the presence of odd pixels.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_d
Enhance the `intel_splitter_adjust_pipe_width` helper to account for
both pixel replication and odd pixels. When the display width is
divided among multiple pipes, extra pixels can make the pipe source
width odd. Since hardware expects an even width, an extra pixel is
added to each pipe to ensure e
With 3 DSC engines we can support 12 slices. With ultra joiner
usecase while dividing the width into 12 slices, we might
end up having odd number of pixels per pipe.
As per Bspec, pipe src size should be even, so an extra pixel is added
in each pipe. For Pipe A and C the odd pixel is added at the
Allow DSC slice count that do not divide the hactive evenly by adding
extra pixels (replicated pixels).
Check if the pixel replication is supported and store the no. of
replicated pixel count in crtc_state.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++
With DSC pixel replication, extra pixels are added in the last slice
of the last pipe. Due to this the total hactive gets increased by few
pixels. Adjust the computation for pipe source width to account for
pixel replication.
These extra pixels will be take care by the Splitter logic in
hardware.
Include the extra pixels added while computing bandwidth with DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915
With 3 VDSC engines and Ultrajoiner, we may encounter a situation where
hactive is not a multiple of slice count. In this case we need to add
extra pixels to the last slice to distribute pixels evenly across
slices.
Add member to store DSC pixel replication when hactive is not divisible
by slice c
Add the extra pixels to the hactive while computing overhead with DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 --
drivers/gpu/drm/i915/display/intel_vdsc.c | 20
Certain resolutions require 12 DSC slices support along with ultrajoiner.
For such cases, the third DSC Engine per Pipe is enabled. Each DSC
Engine processes 1 Slice, resulting in a total of 12 VDSC slices
(4 Pipes * 3 DSC Instances per Pipe).
Add support for 12 DSC slices and 3 DSC engines for suc
Add macro for Pixel replication support with DSC.
Bspec: 49259, 68912
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_device.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/i
According to the DSC spec, the slice width should be chosen such that
the picture width (hactive) is evenly divisible by the slice width.
If not, extra pixels (padding) must be added to the last slice to
ensure all slices have the same width.
Currently, we do not support handling these extra pixel
With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS
registers for the 3rd DSC engine
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +---
drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 6 ++
2 files c
Introduce the register bits to enable the 3rd DSC engine VDSC2.
Add support to read/write these bits.
v2: Only introduce bits that are used and update the subject and commit
message. (Suraj)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
driver
Drop use of LEFT/RIGHT VDSC engine and use VDSC0/VDSC1 instead.
While at it, use REG_BIT macro for the bits.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 8
drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 4 ++--
2 files
At the moment dsc_split represents whether the dsc splitter is used
or not. With 3 DSC engines, the splitter can split into two streams
or three streams.
Instead of representing the splitter's state, it is more effective to
represent the number of DSC streams per pipe.
Replace the `dsc.dsc_split`
For some platforms, the maximum slices per DSC engine is 4, while for
others it is 2. Update the comment to reflect this and clarify that
the 'valid_dsc_slicecount' list represents the valid number of slices
per pipe.
Currently, we are working with 1, and 2 slices per DSC engine,
which works for a
For BMG 3 VDSC engines are supported and each pipe can then support
3 slices. For Ultra joiner cases for modes like 8k@120 Hz we require
ultrajoiner and 3 x 4= 12 slices.
Add support for 3 VDSC engines and 12 DSC slices. Along with this
Pixel replication and Odd pixel considerartions are also requi
== Series Details ==
Series: drm/i915: Use string enable/disable choice helpers
URL : https://patchwork.freedesktop.org/series/140356/
State : warning
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/140356/revisions/1/mbox/ not
found
Instead of drm_err(), use ENGINE_TRACE for tracing.
Signed-off-by: Nitin Gote
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 20 +--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/int
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, September 26, 2024 3:44 PM
> To: Murthy, Arun R ; intel...@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: Re: [PATCH 1/7] drm/i915/histogram: Define regist
Replace the last few remaining instances of string enable(d)/disable(d)
choices with the linux string choice helpers to avoid further
cocci warnings.
Signed-off-by: Sai Teja Pottumuttu
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
On 22-10-2024 22:39, Rodrigo Vivi wrote:
On Tue, Oct 22, 2024 at 03:28:43PM +0200, Andi Shyti wrote:
Hi Badal,
On Tue, Oct 22, 2024 at 06:52:26PM +0530, Badal Nilawar wrote:
Encountering forcewake errors related to render power gating;
Can you please expand your explanation here?
yeap.
== Series Details ==
Series: drm/i915: Allow fastset for change in HDR infoframe (rev3)
URL : https://patchwork.freedesktop.org/series/139293/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15581 -> Patchwork_139293v3
Summar
== Series Details ==
Series: pmu changes
URL : https://patchwork.freedesktop.org/series/140350/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15581 -> Patchwork_140350v1
Summary
---
**SUCCESS**
No regressions foun
== Series Details ==
Series: pmu changes
URL : https://patchwork.freedesktop.org/series/140350/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: pmu changes
URL : https://patchwork.freedesktop.org/series/140350/
State : warning
== Summary ==
Error: dim checkpatch failed
95db02e7c02a pmu changes
-:7: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible
unwrapped commit description?)
#7
Changes in Dynamic Range and Mastering infoframe
should not trigger a full modeset. Therefore, allow
fastset. DP SDP programming is already hooked up in the
fastset flow but HDMI AVI infoframe update is not, add it.
Any other infoframe that can be fastset should be added to
the helper intel_hdmi_fa
By Peter:
git://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git
perf/pmu-unregister
https://lore.kernel.org/all/20241022215210.ga31...@noisy.programming.kicks-ass.net/
To be tested with additional igt tests
Signed-off-by: Lucas De Marchi
---
include/linux/idr.h| 17 +
include
== Series Details ==
Series: drm/i915/gsc: test new GSC 102.1.15.1926 for MTL
URL : https://patchwork.freedesktop.org/series/140338/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15581 -> Patchwork_140338v1
Summary
---
== Series Details ==
Series: drm/i915/gsc: test new GSC 102.1.15.1926 for MTL
URL : https://patchwork.freedesktop.org/series/140338/
State : warning
== Summary ==
Error: dim checkpatch failed
26f806942076 drm/i915/gsc: test new GSC 102.1.15.1926 for MTL
-:25: ERROR:SPACING: space prohibited be
This patch is for testing only. If the testing is ok, the current
mtl_gsc_1.bin binary will be replaced with this one.
Note that the GSC FW macros use the compatibility version, so we can't
use them to produce the path of a binary based on the release version.
Since this is a ci-only patch to test
Quoting Bhadane, Dnyaneshwar (2024-10-21 17:09:00-03:00)
>
>
>> -Original Message-
>> From: Intel-gfx On Behalf Of
>> Gustavo Sousa
>> Sent: Friday, October 18, 2024 2:23 AM
>> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
>> Subject: [PATCH] drm/i915/xe2lpd: Update C
Quoting Jani Nikula (2024-10-21 09:29:30-03:00)
>On Thu, 17 Oct 2024, Gustavo Sousa wrote:
>> There has been an update to the Bspec in which we need to set
>> tx_misc=0x5 field for C20 TX Context programming for HDMI TMDS for
>> Xe2_LPD and newer. That field is mapped to the bits 7:0 of
>> SRAM_GE
Hi Suraj,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20241022]
[cannot apply to drm-xe/drm-xe-next drm-intel/for-linux-next-fixes
drm-tip/drm-tip linus/master v6.12-rc4]
[If your patch is applied to
Quoting Patchwork (2024-10-22 13:53:20-03:00)
>== Series Details ==
>
>Series: drm/i915/xe3lpd: Load DMC
>URL : https://patchwork.freedesktop.org/series/140321/
>State : failure
>
>== Summary ==
>
>CI Bug Log - changes from CI_DRM_15579 -> Patchwork_140321v1
>=
On Mon, Oct 21, 2024 at 04:54:14PM +0300, Jani Nikula wrote:
> Switch to using the new display->platform. members for
> platform identification in display code.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_tv.c | 10 --
> 1 file c
On Mon, Oct 21, 2024 at 04:54:07PM +0300, Jani Nikula wrote:
> Add a structure with a bitfield member for each platform and
> subplatform, and initialize them in platform and subplatform descs.
>
> The structure also contains a bitmap in a union for easier manipulation
> of the bits. This, in turn
On Mon, Oct 21, 2024 at 04:54:08PM +0300, Jani Nikula wrote:
> Facilitate using display->platform.haswell and
> display->platform.haswell_ult etc. for identifying platforms and
> subplatforms.
>
> Merge the platform and subplatform bitmaps together, and check that
> there's no overlap.
>
> v4:
>
On Mon, Oct 21, 2024 at 04:54:09PM +0300, Jani Nikula wrote:
> The display platform enums are not really needed for anything. Remove.
>
> Without the enum, PLATFORM_UNINITIALIZED is also no longer needed for
> keeping the first enum 0.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915
On Mon, Oct 21, 2024 at 04:54:10PM +0300, Jani Nikula wrote:
> Add support for defining aliases for platform groups, such as g4x that
> covers both g45 and gm45.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_display_device.c | 9 +
On Mon, Oct 21, 2024 at 04:54:12PM +0300, Jani Nikula wrote:
> Switch to using the new display->platform. members for
> platform identification in display code.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 40 +---
On Mon, Oct 21, 2024 at 04:54:13PM +0300, Jani Nikula wrote:
> Switch to using the new display->platform. members for
> platform identification in display code.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_pps.c | 47 ++---
Reviewed-by: Clint Taylor
-Clint
On Tue, 2024-10-22 at 12:50 -0300, Gustavo Sousa wrote:
> Load the DMC for Xe3LPD.
>
> Signed-off-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/dr
On Mon, Oct 21, 2024 at 04:54:15PM +0300, Jani Nikula wrote:
> Switch to using the new display->platform. members for
> platform identification in display code.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_vga.c | 4 +---
> 1 file changed
On Mon, Oct 21, 2024 at 04:54:16PM +0300, Jani Nikula wrote:
> Switch to using the new display->platform. members for
> platform identification in display code.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_vblank.c | 11 +--
> 1 file changed, 5 insertions(+),
== Series Details ==
Series: drm/i915/display: Add Wa_16023981245
URL : https://patchwork.freedesktop.org/series/140327/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15579 -> Patchwork_140327v1
Summary
---
**SUCCESS
On Tue, Oct 22, 2024 at 03:28:43PM +0200, Andi Shyti wrote:
> Hi Badal,
>
> On Tue, Oct 22, 2024 at 06:52:26PM +0530, Badal Nilawar wrote:
> > Encountering forcewake errors related to render power gating;
>
> Can you please expand your explanation here?
yeap. More explanation please. All platfor
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140324/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15579 -> Patchwork_140324v1
Summa
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140324/
State : warning
== Summary ==
Error: dim checkpatch failed
cdfb5982a17c drm/i915/gmbus: convert to struct intel_display
f5b020b2bfb3 drm/i915/cx0: con
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140324/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/xe3lpd: Load DMC
URL : https://patchwork.freedesktop.org/series/140321/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15579 -> Patchwork_140321v1
Summary
---
**FAILURE**
Serio
Disable the support for odd panning in x direction.
v2: Replace HSD with WA in commit message [Suraj]
Modified the condition for handling odd panning
v3: Simplified the condition for checking hsub
Using older framework for wa as rev1[Jani]
v4: Modify the condition for hsub [Sai Teja]
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch CRT code over to it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 207 +-
drivers/gpu/drm/i915/display/intel_crt.h | 10 +-
driver
With many of the intel_de_* callers switched over to struct
intel_display, we can remove some of the unnecessary generic wrappers.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_de.h | 46 ++---
1 file changed, 18 insertions(+), 28 deletions(-)
diff --git
There are some unconverted stragglers left in the HDCP API still using
struct drm_i915_private. Convert to struct intel_display.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_driver.c | 7 +++--
drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
drivers/gpu/drm/i915/di
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch ICL DSI code over to it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 444 ---
drivers/gpu/drm/i915/display/icl_dsi.h | 4 +-
drivers
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch HSW IPS code over to it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/hsw_ips.c | 47 ++
1 file changed, 26 insertions(+), 21 deletions(-)
diff --
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch assert_chv_phy_status() and its
callers to it. Main motivation to do just one function is to stop
passing i915 to intel_de_wait(), so its generic wrapper can be removed.
Signed-off-by: Jan
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch DP HDCP code over to it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 88 ++--
1 file changed, 45 insertions(+), 43 deletions(-)
diff --
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch vlv_wait_port_ready() over to
it. The main motivation to do just one function is to stop passing i915
to intel_de_wait(), so its generic wrapper can be removed.
Signed-off-by: Jani Nikula
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch DPIO PHY code over to it.
Signed-off-by: Jani Nikula
---
.../i915/display/intel_display_power_well.c | 19 ++-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 158 +-
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch Cx0 PHY code over to it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 308 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
dri
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch gmbus code over to it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 6 +-
drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
.../drm/i915/display
Convert a random bunch of files over to struct intel_display.
Jani Nikula (11):
drm/i915/gmbus: convert to struct intel_display
drm/i915/cx0: convert to struct intel_display
drm/i915/dpio: convert to struct intel_display
drm/i915/hdcp: further conversion to struct intel_display
drm/i915/
Load the DMC for Xe3LPD.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 48bbbf8f312c..5392b68627ae 1006
Hi Jani,
> Jani Nikula (3):
> drm/i915/pciids: add PVC PCI ID macros
> drm/intel/pciids: rename i915_pciids.h to just pciids.h
> drm/xe: switch to common PCI ID macros
Reviewed-by: Andi Shyti
Andi
Hi Jani,
...
> Could be intel_pciids.h too, but it's already in include/drm/intel
If we met in the coffee corner and you asked me, I would have
said that intel_pciids.h would be better, but I won't complain if
you keep it as it is.
> subdirectory.
...
> -#ifndef _I915_PCIIDS_H
> -#define _I91
== Series Details ==
Series: drm/i915/rc6: Disable RPG during workload execution
URL : https://patchwork.freedesktop.org/series/140315/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15577 -> Patchwork_140315v1
Summary
-
== Series Details ==
Series: drm/i915/rc6: Disable RPG during workload execution
URL : https://patchwork.freedesktop.org/series/140315/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Hi Badal,
On Tue, Oct 22, 2024 at 06:52:26PM +0530, Badal Nilawar wrote:
> Encountering forcewake errors related to render power gating;
Can you please expand your explanation here?
> therefore, disable it during workload execution.
... and here.
> Cc: Chris Wilson
> Signed-off-by: Badal Nila
On Tue, Oct 22, 2024 at 04:04:11PM +0300, Imre Deak wrote:
> Hi CI team,
>
> On Tue, Oct 22, 2024 at 12:27:08PM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915: Write source OUI for non-eDP sinks (rev3)
> > URL : https://patchwork.freedesktop.org/series/140061/
> > Sta
== Series Details ==
Series: mtd: add driver for Intel discrete graphics
URL : https://patchwork.freedesktop.org/series/140306/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15576 -> Patchwork_140306v1
Summary
---
**
On 11-10-2024 16:02, Raag Jadav wrote:
G8 power state entry is disabled due to a limitation on DG2, so we
enable it from driver with Wa_14022698537. Fow now we enable it for
all DG2 devices with the exception of a few, for which, we enable
only when paired with whitelisted CPU models.
v2: Fix
Hi CI team,
On Tue, Oct 22, 2024 at 12:27:08PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Write source OUI for non-eDP sinks (rev3)
> URL : https://patchwork.freedesktop.org/series/140061/
> State : failure
the failure is unrelated, see below.
> == Summary ==
>
> CI
Encountering forcewake errors related to render power gating;
therefore, disable it during workload execution.
Cc: Chris Wilson
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 18 +-
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 1 +
2 files changed,
== Series Details ==
Series: mtd: add driver for Intel discrete graphics
URL : https://patchwork.freedesktop.org/series/140306/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: mtd: add driver for Intel discrete graphics
URL : https://patchwork.freedesktop.org/series/140306/
State : warning
== Summary ==
Error: dim checkpatch failed
65e51895699b mtd: add driver for intel graphics non-volatile memory device
-:68: WARNING:FILE_PATH_CHANGES:
On Fri, 04 Oct 2024, Christophe JAILLET wrote:
> Le 04/10/2024 à 11:35, Jani Nikula a écrit :
>> On Thu, 03 Oct 2024, Christophe JAILLET
>> wrote:
>>> kstrdup_const() and kfree_const() can be confusing in code built as a
>>> module. In such a case, it does not do what one could expect from the n
On Tue, 22 Oct 2024, Zhi Wang wrote:
> Reviewed-by: Zhi Wang
>
>
> Sorry for the late reply as I was on vacation.
Thanks for the reviews, pushed to drm-intel-next.
BR,
Jani.
>
> On Tue, Oct 22, 2024, 2:50 PM Kandpal, Suraj
> wrote:
>
>>
>>
>> > -Original Message-
>> > From: Intel-gfx
== Series Details ==
Series: drm/i915: Write source OUI for non-eDP sinks (rev3)
URL : https://patchwork.freedesktop.org/series/140061/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15576 -> Patchwork_140061v3
Summary
-
== Series Details ==
Series: drm/i915: Write source OUI for non-eDP sinks (rev3)
URL : https://patchwork.freedesktop.org/series/140061/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm
== Series Details ==
Series: drm/i915 & drm/xe: shared PCI ID macros (rev2)
URL : https://patchwork.freedesktop.org/series/138110/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15576 -> Patchwork_138110v2
Summary
---
== Series Details ==
Series: drm/i915 & drm/xe: shared PCI ID macros (rev2)
URL : https://patchwork.freedesktop.org/series/138110/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bito
== Series Details ==
Series: drm/i915 & drm/xe: shared PCI ID macros (rev2)
URL : https://patchwork.freedesktop.org/series/138110/
State : warning
== Summary ==
Error: dim checkpatch failed
d5cfb1f8eda4 drm/i915/pciids: add PVC PCI ID macros
-:30: ERROR:COMPLEX_MACRO: Macros with complex value
Hi Jani,
Thank you for the review.
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, October 9, 2024 2:59 PM
> To: Borah, Chaitanya Kumar ; intel-
> g...@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Deak, Imre ; Shankar, Uma
> ; ville.syrj...@linux.intel.com
> Su
Reviewed-by: Zhi Wang
Sorry for the late reply as I was on vacation.
On Tue, Oct 22, 2024, 2:50 PM Kandpal, Suraj
wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> Jani
> > Nikula
> > Sent: Monday, September 30, 2024 7:24 PM
> > To: intel-gfx@lists.freedesktop.org;
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Monday, September 30, 2024 7:24 PM
> To: intel-gfx@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [RESEND] drm/i915/gvt: use macros from drm_dp.h instead of
> duplication
On Mon, 21 Oct 2024, Gustavo Sousa wrote:
> In order to be able to use the DMC wakelock, we also need to know that
> the display hardware has support for DMC, which is a runtime info.
> Define HAS_DMC_WAKELOCK(), which checks for both DMC availability and IP
> version, and use it in place of direc
Switch to the shared PCI ID macros in drm/intel/pciids.h. Remove
xe_pciids.h.
Cc: Joonas Lahtinen
Cc: Lucas De Marchi
Cc: Rodrigo Vivi
Cc: Thomas Hellström
Cc: Tvrtko Ursulin
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/xe_pci.c | 53
include/drm/intel/xe_pciids.h | 234 ---
Quoting Gustavo Sousa (2024-10-21 19:27:26-03:00)
>There are extra registers that require the DMC wakelock when specific
>dynamic DC states are in place. Add the table ranges for them and use
>the correct table depending on the allowed DC states.
>
>Bspec: 71583
For anyone who is reviewing this an
Quoting Jani Nikula (2024-10-22 05:03:50-03:00)
>On Mon, 21 Oct 2024, Gustavo Sousa wrote:
>> There are extra registers that require the DMC wakelock when specific
>> dynamic DC states are in place. Add the table ranges for them and use
>> the correct table depending on the allowed DC states.
>>
>
Quoting Jani Nikula (2024-10-22 05:03:21-03:00)
>On Mon, 21 Oct 2024, Gustavo Sousa wrote:
>> There are extra registers that require the DMC wakelock when specific
>> dynamic DC states are in place. Add the table ranges for them and use
>> the correct table depending on the allowed DC states.
>>
>
Quoting Jani Nikula (2024-10-22 06:37:51-03:00)
>On Mon, 21 Oct 2024, Gustavo Sousa wrote:
>> In order to be able to use the DMC wakelock, we also need to know that
>> the display hardware has support for DMC, which is a runtime info.
>> Define HAS_DMC_WAKELOCK(), which checks for both DMC availab
Add auxiliary driver for intel discrete graphics
non-volatile memory device.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
MAINTAINERS| 7 ++
drivers/mtd/devices/Kconfig|
Quoting Jani Nikula (2024-10-22 06:34:44-03:00)
>On Mon, 21 Oct 2024, Gustavo Sousa wrote:
>> Some display MMIO transactions for offsets in the range that requires
>> the DMC wakelock happen in atomic context (this has been confirmed
>> during tests on PTL). That means that we need to use a non-sl
In intel-dg, there is no access to the spi controller,
the information is extracted from the descriptor region.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd-intel-dg.c | 199 +
Implement read(), erase() and write() functions.
CC: Lucas De Marchi
CC: Rodrigo Vivi
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Co-developed-by: Vitaly Lubart
Signed-off-by: Vitaly Lubart
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd-intel-dg.c | 199 ++
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +---
drivers/gpu/drm/xe/xe_nvm.c | 33 ++
Enable access to internal non-volatile memory on
DGFX devices via a child device.
The nvm child device is exposed via auxiliary bus.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/Make
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