== Series Details ==
Series: Use trans push mechanism to generate frame change event
URL : https://patchwork.freedesktop.org/series/139830/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15510 -> Patchwork_139830v1
Summary
-
base: git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:
https://lore.kernel.org/r/20241008082327.342020-7-vinod.govindapillai%40intel.com
patch subject: [PATCH 6/9] drm/i915/display: iterare through channels if no
feasible frequencies
config: x86_64-randconfig-161-20241009
== Series Details ==
Series: Use trans push mechanism to generate frame change event
URL : https://patchwork.freedesktop.org/series/139830/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include
On LunarLake and onwards we are using vrr send push mechanism to trigger
frame change event. Due to this we need to trigger it using
intel_vrr_psr_send_push provided by VRR code on legacy cursor update.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_cursor.c | 5 +
1 fi
Add own interface for PSR usage to perform push on frontbuffer tracking
invalidate and flush call backs. Use this new interface from PSR code.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 ++-
drivers/gpu/drm/i915/display/intel_vrr.c | 18 ++
There is unnecessary complexity in frontbuffer tracking invalidate and
flush callbacks. Simplify them a bit with some minor changes to sequences:
Invalidate:
1. Additionally write single full frame bit when selective fetch is
enabled. This should be ok as continuous full frame bit is already set.
Currently vrr code is overwriting possibly set PSR PR Frame Change Enable
bit in TRANS_PUSH register. Avoid this by using rmw instead of write.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_vrr.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/d
psr_force_hw_tracking_exit is misleading name as it is used for PSR1, PSR2
HW tracking and PSR2 selective fetch. Due to this rename it as
psr_force_exit.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
In Lunarlake and onwards it is possible to generate "PSR frame change"
event using TRANS_PUSH mechanism. Implement function to enable this and
take PSR into account in intel_vrr_send_push.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 6
drivers/gpu/drm/i915/
Add TRANS_PUSH register bit LNL_TRANS_PUSH_PSR_PR_EN definition for PSR
usage.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
b/drivers/gpu/drm/i915/display/intel_v
Currently we are using "automatic" frame change event generation. The
event is generated by any access to plane or pipe registers.
We have option to use "PSR PR Frame Change Enable" bit in TRANS_PUSH
register to enable frame change event generation on trans push. When
this bit is set "automatic" f
On Wed, 2024-10-09 at 17:15 +0300, Jani Nikula wrote:
> On Wed, 09 Oct 2024, Jouni Högander wrote:
> > We are about to change meaning of vblank_enabled to fix Panel
> > Replay vblank
> > workaround. For sake of clarity we need to rename it.
> > Vblank_enabled is
> > used for i915gm/i945gm vblank i
== Series Details ==
Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev3)
URL : https://patchwork.freedesktop.org/series/138257/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15510 -> Patchwork_138257v3
Summary
== Series Details ==
Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev3)
URL : https://patchwork.freedesktop.org/series/138257/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/inclu
== Series Details ==
Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev3)
URL : https://patchwork.freedesktop.org/series/138257/
State : warning
== Summary ==
Error: dim checkpatch failed
0431e6484d80 Add bits for link_n_exended for DISPLAY >= 14
365533a789eb drm/i915/display: Lim
Hi all,
After merging the drm-misc tree, today's linux-next build (htmldocs)
produced these warnings:
include/drm/ttm/ttm_device.h:255: warning: Incorrect use of kernel-doc format:
* @unevictable Buffer objects which are pinned or swapped and as such
include/drm/ttm/ttm_device.h:270: wa
Hi all,
After merging the drm-misc tree, today's linux-next build (htmldocs)
produced these warnings:
drivers/gpu/drm/drm_mipi_dsi.c:1533: warning: Excess function parameter 'dsi'
description in 'mipi_dsi_compression_mode_multi'
drivers/gpu/drm/drm_mipi_dsi.c:1533: warning: Function parameter or
== Series Details ==
Series: Vrr refactoring and panel replay workaround (rev5)
URL : https://patchwork.freedesktop.org/series/138232/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15510 -> Patchwork_138232v5
Summary
--
== Series Details ==
Series: Vrr refactoring and panel replay workaround (rev5)
URL : https://patchwork.freedesktop.org/series/138232/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/
> -Original Message-
> From: Atwood, Matthew S
> Sent: Thursday, October 10, 2024 4:36 AM
> To: Kandpal, Suraj
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Kandpal,
> Suraj
> Subject: Re: [PATCH 09/10] drm/i915/xe3lpd: Add check to see if edp over
> type c is
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, October 9, 2024 3:20 PM
> To: Kandpal, Suraj ; intel-
> x...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Kandpal, Suraj
>
> Subject: Re: [PATCH] drm/i915/hdcp: Move dig_port assignment lowe
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, October 9, 2024 1:09 PM
> To: Atwood, Matthew S ; intel-
> x...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Kandpal, Suraj ; Atwood, Matthew S
>
> Subject: Re: [PATCH 06/10] drm/i915/xe3lpd: Add macro to choos
> -Original Message-
> From: Roper, Matthew D
> Sent: Wednesday, October 9, 2024 5:07 AM
> To: Atwood, Matthew S
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Kandpal,
> Suraj
> Subject: Re: [PATCH 06/10] drm/i915/xe3lpd: Add macro to choose
> HDCP_LINE_REKEY
Handle the bypass logic for the M/N ratio limit for DP.
Calculate the M/N ratio, check if it can bypass the limit, and set the
appropriate flags for the workaround.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
drivers/gpu/drm/i915/display/intel_display.h
To support Link M/N ratio between 10.0 and 15.0, for some BMG ultrajoiner
cases we need Wa_14021768792.
To bypass the hardware limitation within the Timing Generator DDA (TGDDA),
we need to program the LINKM and LINKN registers as defined in
the WA. Along with this we also need relvant bits in HDM
As per Bspec:49266 for DISPLAY > 12 which support higher
link rates have a limitation:
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
Modify the helper to compute m_n, to check for the max l
LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA
(Bspec:50488).
Add support for these extra bits.
v2: Drop extra link_n_ext member. (Jani)
v3: Avoid link_n_ext in set_m_n helper. (Jani)
Signed-off-by: Ankit Nautiyal
--
For Platforms that support higher link rates, there is a limitation on
Link M /Link N ratio.
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
For BMG Wa_14021768792 helps to bypass this limitat
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, October 9, 2024 2:21 PM
> To: Kandpal, Suraj
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Shankar,
> Uma ; Borah, Chaitanya Kumar
>
> Subject: Re: [PATCH] drm/i915/color: Use correct variable to lo
Add helper to check if vrr is possible based on flipline
is computed.
--v1:
return just flipline instead using ternary operator [Jonathan, Ville].
Signed-off-by: Mitul Golani
Reviewed-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
drivers/gpu/drm/i915/display/int
From: Animesh Manna
As vrr guardband calculation is dependent on modified
vblank start so better to compute late after all
vblank adjustement.
v1: Initial version.
v2: Split in a separate patch from panel-replay workaround. [Ankit]
v3: Add a function for late vrr related computation. [Ville]
v4:
From: Animesh Manna
Panel Replay VSC SDP not getting sent when VRR is enabled
and W1 and W2 are 0. So Program Set Context Latency in
TRANS_SET_CONTEXT_LATENCY register to at least a value of 1.
The same is applicable for PSR1/PSR2 as well.
HSD: 14015406119
v1: Initial version.
v2: Update timing
Refactor VRR compute config to account for Panel replay workaround
for VSC SDP.
Previous Patch series links:
https://patchwork.freedesktop.org/series/135629/
https://patchwork.freedesktop.org/series/135851/
https://patchwork.freedesktop.org/series/138232/
Animesh Manna (2):
drm/i915/vrr: Split
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Wednesday, October 9, 2024 4:32 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 1/2] drm/i915/dp_mst: Handle error during DSC BW
> overhead/slice calculation
>
> The MST branch device may not support the
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Wednesday, October 9, 2024 4:32 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 2/2] drm/i915/dp_mst: Don't require DSC hblank quirk for a
> non-DSC compatible mode
>
> If an MST branch device doesn't su
> -Original Message-
> From: Atwood, Matthew S
> Sent: Thursday, October 10, 2024 4:35 AM
> To: Kandpal, Suraj
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Kandpal,
> Suraj
> Subject: Re: [PATCH 10/10] drm/i915/xe3lpd: Add powerdown value of eDP
> over type c
== Series Details ==
Series: drm/xe/display: Fix memory leak in parse_lfp_panel_dtd()
URL : https://patchwork.freedesktop.org/series/139819/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15510 -> Patchwork_139819v1
Summary
The function parse_lfp_panel_dtd() is called when the driver
attempts to initialize the eDP connector, and it allocates memory,
which is recorded in panel->vbt.lfp_vbt_mode. However, since no
eDP panel is connected, the driver fails at intel_edp_init_dpcd()
and follows the failure path. Unfortunate
On Wed, Oct 09, 2024 at 10:53:56AM +0300, Jani Nikula wrote:
> On Tue, 08 Oct 2024, Matt Atwood wrote:
> > From: Suraj Kandpal
> >
> > Read PICA register to see if edp over type C is possible and then
> > add the appropriate tables for it.
>
> There's clearly more to be done for the feature than
On Wed, Oct 09, 2024 at 10:57:03AM +0300, Jani Nikula wrote:
> On Tue, 08 Oct 2024, Matt Atwood wrote:
> > From: Suraj Kandpal
> >
> > Add condition for P2.PG power down value.
> >
> > Bspec: 74494
> > Signed-off-by: Suraj Kandpal
> > Signed-off-by: Matt Atwood
> > ---
> > drivers/gpu/drm/i915
Hi Nitin,
On Thu, Oct 03, 2024 at 07:40:44PM +0530, Nitin Gote wrote:
> From: Chris Wilson
>
> On Haswell, in particular, we see an issue where resets fails because
> the engine resumes from an incorrect RING_HEAD. Since the RING_HEAD
> doesn't point to the remaining requests to re-run, but may
-Original Message-
From: Deak, Imre
Sent: Wednesday, October 9, 2024 2:26 PM
To: Cavitt, Jonathan
Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 1/4] drm/i915/dp: Assume panel power is off if runtime
suspended
>
> On Wed, Oct 09, 2024 at 11:3
== Series Details ==
Series: drm/xe: Fix HPD interrupt enabling during runtime resume
URL : https://patchwork.freedesktop.org/series/139813/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15510 -> Patchwork_139813v1
Summary
== Series Details ==
Series: drm/xe: Fix HPD interrupt enabling during runtime resume
URL : https://patchwork.freedesktop.org/series/139813/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, Oct 09, 2024 at 11:35:56PM +0300, Cavitt, Jonathan wrote:
> -Original Message-
> From: Intel-xe On Behalf Of Imre Deak
> Sent: Wednesday, October 9, 2024 12:44 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Subject: [PATCH v2 1/4] drm/i915/dp: Assume pan
== Series Details ==
Series: drm/i915: Async flip + compression, and some plane cleanups
URL : https://patchwork.freedesktop.org/series/139807/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15509 -> Patchwork_139807v1
Summa
-Original Message-
From: Intel-gfx On Behalf Of Imre Deak
Sent: Wednesday, October 9, 2024 12:44 PM
To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 2/4] drm/i915/dp: Disable unnecessary HPD polling for eDP
>
> A registered eDP connector is considered
== Series Details ==
Series: drm/i915: Async flip + compression, and some plane cleanups
URL : https://patchwork.freedesktop.org/series/139807/
State : warning
== Summary ==
Error: dim checkpatch failed
0842b69545cf drm/i915: Allow async flips with render compression on TGL+
5dc9b779514e drm/i
== Series Details ==
Series: drm/i915: Async flip + compression, and some plane cleanups
URL : https://patchwork.freedesktop.org/series/139807/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/inc
-Original Message-
From: Intel-xe On Behalf Of Imre Deak
Sent: Wednesday, October 9, 2024 12:44 PM
To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 1/4] drm/i915/dp: Assume panel power is off if runtime
suspended
>
> If the device is runtime suspende
Reviewed-by: Clint Taylor
-Clint
On Tue, 2024-10-08 at 15:37 -0700, Matt Atwood wrote:
> From: Suraj Kandpal
>
> From DISPLAY_VER() >= 30 C20 PHY consolidated programming table of
> DP and eDP been merged and now use the same rates and values. eDP
> over TypeC has also been introduced.
> More
Atm the display HPD interrupts that got disabled during runtime
suspend, are re-enabled only if d3cold is enabled. Fix things by
also re-enabling the interrupts if d3cold is disabled.
Cc: Rodrigo Vivi
Reviewed-by: Jonathan Cavitt
Signed-off-by: Imre Deak
---
drivers/gpu/drm/xe/display/xe_displ
For clarity separate the d3cold and non-d3cold runtime PM handling. The
only change in behavior is disabling polling later during runtime
resume. This shouldn't make a difference, since the poll disabling is
handled from a work, which could run at any point wrt. the runtime
resume handler. The work
A registered eDP connector is considered to be always connected, so it's
unnecessary to poll it for a connect/disconnect event. Polling it
involves AUX accesses toggling the panel power, which in turn can
generate a spurious short HPD pulse and possibly a new poll cycle via
the short HPD handler ru
This is v2 of [1], fixing a failure in igt/kms_pm_rpm/universal-planes
reported by CI.
[1] https://lore.kernel.org/all/20241007140531.1044630-1-imre.d...@intel.com
Cc: Rodrigo Vivi
Cc: Jonathan Cavitt
Imre Deak (4):
drm/i915/dp: Assume panel power is off if runtime suspended
drm/i915/dp: D
If the device is runtime suspended the eDP panel power is also off.
Ignore a short HPD on eDP if the device is suspended accordingly,
instead of checking the panel power state via the PPS registers for the
same purpose. The latter involves runtime resuming the device
unnecessarily, in a frequent sc
On 10/4/2024 6:31 AM, Vignesh Raman wrote:
Add job that executes the IGT test suite for sm8350-hdk.
Signed-off-by: Vignesh Raman
---
drivers/gpu/drm/ci/arm64.config | 7 +-
drivers/gpu/drm/ci/build.sh | 1 +
drivers/gpu/drm/ci/test.yml
== Series Details ==
Series: drm/i915/display: Remove kstrdup_const() and kfree_const() usage (rev2)
URL : https://patchwork.freedesktop.org/series/139525/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15508 -> Patchwork_139525v2
===
== Series Details ==
Series: drm/i915: remove all IS__GT() macros (rev2)
URL : https://patchwork.freedesktop.org/series/139306/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15508 -> Patchwork_139306v2
Summary
---
**
On Wed, Oct 09, 2024 at 07:42:40PM +0300, Raag Jadav wrote:
> On Wed, Oct 09, 2024 at 04:05:20PM +0300, Jani Nikula wrote:
> > On Wed, 09 Oct 2024, Raag Jadav wrote:
> > > On Tue, Oct 08, 2024 at 08:24:42PM +0300, Jani Nikula wrote:
> > >> On Mon, 07 Oct 2024, Raag Jadav wrote:
> > >> > +
> > >>
== Series Details ==
Series: drm/i915: remove all IS__GT() macros (rev2)
URL : https://patchwork.freedesktop.org/series/139306/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: remove all IS__GT() macros (rev2)
URL : https://patchwork.freedesktop.org/series/139306/
State : warning
== Summary ==
Error: dim checkpatch failed
a59ec96d4cdd drm/i915: remove all IS__GT() macros
-:135: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915'
== Series Details ==
Series: Align framebuffers according to what display minimum alignment states
URL : https://patchwork.freedesktop.org/series/139795/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15508 -> Patchwork_139795v1
=
== Series Details ==
Series: Align framebuffers according to what display minimum alignment states
URL : https://patchwork.freedesktop.org/series/139795/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Ville Syrjälä
Split skl_get_plane_caps() into four variants:
skl_plane_caps(), glk_plane_caps(), icl_plane_caps(),
tgl_plane_caps().
Makes it easier to figure out what is actually going on there.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/skl_universal_plane.c| 81 +++
From: Ville Syrjälä
Move the xe AUX neutering out from skl_get_plane_caps() into the
caller so that it'll be easier to refactor skl_get_plane_caps()
into a more readable shape. This isn't really hardware specific
anyway, and just some kind of bug/misfeature of xe.
Signed-off-by: Ville Syrjälä
-
From: Ville Syrjälä
Wa_22011186057 (some CCS problem) only affected ADL A-stepping,
which I presume is pre-production hw. Drop the dead code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/g
From: Ville Syrjälä
TGL+ should no longer need any VT-d scanout workarounds.
Don't apply any.
Not 100% sure whether pre-SNB might also suffer from this. The
workaround did originate on SNB but who knows if it was just
never caught before that. Not that I ever managed to enable
VT-d any older har
From: Ville Syrjälä
Rename vlv_primary_min_alignment() to vlv_plane_min_alignment()
and use it to replace vlv_sprite_min_alignment() since the
behaviour is now identical when the plane init doesn't set up
any async flips stuff.
Technically VLV/CHV sprites do support async flips, so this
also mak
From: Ville Syrjälä
Async flips often require bigger alignment that sync flips.
Currently we have HAS_ASYNC_FLIPS() checks strewn about to
inidcate that async flips are generally supported and thus
we want more alignment. Switch that over to using
intel_plane_can_async_flip() so that we can handl
From: Ville Syrjälä
Move the "does this modifier support async flips?" check
to be handled by the platform specific plane code instead
of having a big mess in common code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 9 +++
.../gpu/drm/i915/display/intel_at
From: Ville Syrjälä
Apparently ICL can do async flips with CCS. In fact it already
seems to work on GLK, but apparently can lead to underruns there
so we'll only enable it for ICL.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 21 +++-
1 file c
From: Ville Syrjälä
Looks like CCS + async flips has been a thing for a while now.
Enable this for TGL+ render compression modifiers.
Note that we can't update AUX_DIST during async flips we must
check to make sure it remains unchanged.
We also can't do clear color. Supposedly there was some at
From: Ville Syrjälä
Enable async flips with compressed buffers on icl+, disable
the VT-d scanout workarounds for TGL+, and follow up with
some cleanups to make the code less messy.
Ville Syrjälä (9):
drm/i915: Allow async flips with render compression on TGL+
drm/i915: Allow async flips with
Hi Dave, Simona,
Here's drm-misc-next for v6.13!
drm-misc-next-2024-10-09:
drm-misc-next for v6.13:
UAPI Changes:
- Add drm fdinfo support to panthor, and add sysfs knob to toggle.
Cross-subsystem Changes:
- Convert fbdev drivers to use backlight power constants.
- Some small dma-fence fixes.
-
Hi Tejas,
On 2024-10-09 at 15:26:08 +0530, Tejas Upadhyay wrote:
one more nit, imho a patch with new test should have in subject
tests/intel: Add xe_pci_membarrier test
Also see nit about a test name.
> We want to make sure that direct mmap mapping of physical
> page at doorbell space and whole
-Original Message-
From: Intel-gfx On Behalf Of
Juha-Pekka Heikkila
Sent: Wednesday, October 9, 2024 8:20 AM
To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Juha-Pekka Heikkila
Subject: [PATCH 2/2] drm/xe/display: align framebuffers according to hw
requirements
>
Hi Jani,
On 2024-10-09 at 15:02:10 +0300, Jani Nikula wrote:
> On Wed, 09 Oct 2024, Kamil Konieczny wrote:
> > Hi Tejas,
> > On 2024-10-09 at 15:26:08 +0530, Tejas Upadhyay wrote:
> >> We want to make sure that direct mmap mapping of physical
> >> page at doorbell space and whole page is accessibl
-Original Message-
From: Intel-xe On Behalf Of Juha-Pekka
Heikkila
Sent: Wednesday, October 9, 2024 8:20 AM
To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: Juha-Pekka Heikkila
Subject: [PATCH 1/2] drm/xe: add interface to request physical alignment for
buffer obj
On 05-10-2024 02:38, Clint Taylor wrote:
Some devices NAK DPCD writes to the SOURCE OUI (0x300) DPCD registers.
Reduce the log level priority to prevent dmesg noise for these devices.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertio
On Thu, Aug 29, 2024 at 08:38:12AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/mtl: Update PLL c20 phy value for DP uhbr20 (rev2)
> URL : https://patchwork.freedesktop.org/series/137844/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_15307_full
On Wed, 09 Oct 2024, Raag Jadav wrote:
> On Wed, Oct 09, 2024 at 04:05:20PM +0300, Jani Nikula wrote:
>> On Wed, 09 Oct 2024, Raag Jadav wrote:
>> > On Tue, Oct 08, 2024 at 08:24:42PM +0300, Jani Nikula wrote:
>> >> On Mon, 07 Oct 2024, Raag Jadav wrote:
>> >> > +
>> >> > +/* Wa_14022698589:dg2
On Wed, Oct 09, 2024 at 04:05:20PM +0300, Jani Nikula wrote:
> On Wed, 09 Oct 2024, Raag Jadav wrote:
> > On Tue, Oct 08, 2024 at 08:24:42PM +0300, Jani Nikula wrote:
> >> On Mon, 07 Oct 2024, Raag Jadav wrote:
> >> > +
> >> > +/* Wa_14022698589:dg2 */
> >> > +static void intel_enable_g8(struct i
On Wed, Oct 09, 2024 at 06:19:47PM +0300, Juha-Pekka Heikkila wrote:
> Align framebuffers in memory according to hw requirements instead of
> default page size alignment.
>
> Signed-off-by: Juha-Pekka Heikkila
> ---
> drivers/gpu/drm/xe/display/xe_fb_pin.c | 57 --
> 1 fi
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/display: Add own counter for
Panel Replay vblank workaround
URL : https://patchwork.freedesktop.org/series/139784/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15505 -> Patchwork_139784v1
===
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/display: Add own counter for
Panel Replay vblank workaround
URL : https://patchwork.freedesktop.org/series/139784/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won'
On Tue, 08 Oct 2024, Chaitanya Kumar Borah
wrote:
> From PTL, FEC_DECODE_EN sequence can be sent to a DPRX independent
> of TRANS_CONF enable. This allows us to re-issue an FEC_DECODE_EN
> sequence without re-doing the whole mode set sequence. This separate
> control over FEC_ECODE_EN/DIS sequenc
Align framebuffers in memory according to hw requirements instead of
default page size alignment.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 57 --
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/xe/disp
Add xe_bo_create_pin_map_at_aligned() which augment
xe_bo_create_pin_map_at() with alignment parameter allowing to pass
required alignemnt if it differ from default.
Signed-off-by: Juha-Pekka Heikkila
---
.../compat-i915-headers/gem/i915_gem_stolen.h | 2 +-
drivers/gpu/drm/xe/xe_bo.c
Here added interface to request physical alignemnt for BOs and
use it to align framebuffers according to what display code
min_align says.
/Juha-Pekka
Juha-Pekka Heikkila (2):
drm/xe: add interface to request physical alignment for buffer objects
drm/xe/display: align framebuffers according t
-Original Message-
From: Intel-gfx On Behalf Of Jouni
Högander
Sent: Wednesday, October 9, 2024 6:42 AM
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrj...@linux.intel.com; jani.nik...@linux.intel.com; Hogander, Jouni
Subject: [PATCH v2 2/2] drm/i915/display: Fix Panel Replay vblank e
-Original Message-
From: Intel-gfx On Behalf Of Jouni
Högander
Sent: Wednesday, October 9, 2024 6:42 AM
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrj...@linux.intel.com; jani.nik...@linux.intel.com; Hogander, Jouni
Subject: [PATCH v2 1/2] drm/i915/display: Add own counter for Panel
On Tue, 08 Oct 2024, Ville Syrjälä wrote:
> On Mon, Oct 07, 2024 at 09:43:47AM +0200, Thomas Zimmermann wrote:
>> Hi
>>
>> Am 03.10.24 um 13:33 schrieb Ville Syrjala:
>> > From: Ville Syrjälä
>> >
>> > Replace the 'unsigned int i' footguns with plain old signed
>> > int. Avoids accidents if/when
On Wed, 09 Oct 2024, Jouni Högander wrote:
> We are about to change meaning of vblank_enabled to fix Panel Replay vblank
> workaround. For sake of clarity we need to rename it. Vblank_enabled is
> used for i915gm/i945gm vblank irq workaround as well -> instead of rename
> add new counter named as
ry.h:617)
[ 12.756757][ T116] ? drm_mode_copy
(kbuild/src/consumer/drivers/gpu/drm/drm_modes.c:1422) drm
The kernel config and materials to reproduce are available at:
https://download.01.org/0day-ci/archive/20241009/202410091649.1353a717-oliver.s...@intel.com
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Quoting Govindapillai, Vinod (2024-10-09 10:09:45-03:00)
>Hi Matt,
>
>Probably you missed one change...
>
>On Tue, 2024-10-08 at 15:37 -0700, Matt Atwood wrote:
>> From: Matt Roper
>>
>> There are some minor changes to pmdemand handling on Xe3:
>> - Active scalers are no longer tracked. We can
== Series Details ==
Series: series starting with [1/2] drm/i915/dp_mst: Handle error during DSC BW
overhead/slice calculation
URL : https://patchwork.freedesktop.org/series/139771/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15502 -> Patchwork_139771v1
Hi,
On Tue, 8 Oct 2024, Vinod Govindapillai wrote:
> After pruning the sad audio frequency list, if there are no
> supported audio frequencies left, audio cannot be supported.
> So mark has_audio accordingly.
[...]
> @@ -823,9 +824,13 @@ bool intel_audio_compute_eld_config(struct
> drm_connector
Currently workaround is not applied when vblank is enabled on crtc that
needs the workaround if vblank is already enabled for another crtc that
doesn't need the workaround. Fix this by increasing counter only if crtc
needs the workaround.
Fixes: aa451abcffb5 ("drm/i915/display: Prevent DC6 while v
We are about to change meaning of vblank_enabled to fix Panel Replay vblank
workaround. For sake of clarity we need to rename it. Vblank_enabled is
used for i915gm/i945gm vblank irq workaround as well -> instead of rename
add new counter named as vblank_wa_pipes.
v2:
- s/vblank_wa_pipes/vblank_w
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