+dri-devel
> -Original Message-
> From: Kulkarni, Vandita
> Sent: Tuesday, September 3, 2024 10:54 AM
> To: Arun R Murthy ; intel-
> g...@lists.freedesktop.org; drm-devel@lists.freedesktop
> Cc: Murthy, Arun R
> Subject: RE: [PATCHv2 3/5] Add crtc properties for global histogram
>
> > --
> -Original Message-
> From: Intel-gfx On Behalf Of Arun
> R Murthy
> Sent: Wednesday, August 21, 2024 3:54 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCHv2 3/5] Add crtc properties for global histogram
>
> CRTC properties have been added for enable/disab
On Mon, 2024-09-02 at 11:33 +0300, Jani Nikula wrote:
> On Mon, 02 Sep 2024, Jouni Högander wrote:
> > In commit "drm/i915/display: Increase number of fast wake precharge
> > pulses"
> > we were increasing Fast Wake sync pulse length to fix problems
> > observed on
> > Dell Precision 5490 laptop w
Hi Ankit,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20240902]
[cannot apply to drm-intel/for-linux-next-fixes linus/master v6.11-rc6]
[If your patch is applied to the wrong git
On Mon, Sep 02, 2024 at 08:13:59PM GMT, Jani Nikula wrote:
There's considerable overlap in i915 and xe PCI ID macros, and (as can
be seen in this series) they get updated out of sync. With i915 display
continuing to use PCI IDs for platforms that i915 core does not support,
humn.. but display i
== Series Details ==
Series: drm/i915 & drm/xe: shared PCI ID macros
URL : https://patchwork.freedesktop.org/series/138110/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15343 -> Patchwork_138110v1
Summary
---
**SUCC
== Series Details ==
Series: drm/i915 & drm/xe: shared PCI ID macros
URL : https://patchwork.freedesktop.org/series/138110/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./arch/x86/include/asm/bitops.h:
== Series Details ==
Series: drm/i915 & drm/xe: shared PCI ID macros
URL : https://patchwork.freedesktop.org/series/138110/
State : warning
== Summary ==
Error: dim checkpatch failed
4c49328848e5 drm/i915/pciids: use designated initializers in INTEL_VGA_DEVICE()
ecd7fe3734dc drm/i915/pciids: s
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev5)
URL : https://patchwork.freedesktop.org/series/134383/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15341_full -> Patchwork_134383v5_full
Switch to the shared PCI ID macros in drm/intel/pciids.h. Remove
xe_pciids.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/xe_pci.c | 51
include/drm/intel/xe_pciids.h | 222 --
2 files changed, 22 insertions(+), 251 deletions(-)
delete mode 1006
In preparation of sharing the PCI ID macros between i915 and xe, rename
i915_pciids.h to pciids.h.
Signed-off-by: Jani Nikula
---
Could be intel_pciids.h too, but it's already in include/drm/intel
subdirectory.
---
arch/x86/kernel/early-quirks.c | 2 +-
drivers/gpu/drm/i91
The xe PCI ID macros are a subset of the i915 PCI IDs macros, apart from
the PVC PCI IDs (naturally, because i915 does not and will not support
PVC). In preparation of using a shared file, add PVC PCI IDs to
i915_pciids.h.
Signed-off-by: Jani Nikula
---
include/drm/intel/i915_pciids.h | 16 +
Avoid including PCI IDs for one platform to the PCI IDs of another. It's
more clear to deal with them completely separately at the PCI ID macro
level.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
include/drm/intel/xe_pciids.h | 13 -
2 files changed, 9 inserti
Avoid including PCI IDs for one platform to the PCI IDs of another. It's
more clear to deal with them completely separately at the PCI ID macro
level.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
include/drm/intel/xe_pciids.h | 1 -
2 files changed, 1 insertion(+), 1 delet
Similar to commit 425b463859ed ("drm/i915: Update ADL-N PCI IDs").
Signed-off-by: Jani Nikula
---
include/drm/intel/xe_pciids.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/drm/intel/xe_pciids.h b/include/drm/intel/xe_pciids.h
index 73d972a8aca1..41617c5ac6ab 10
Avoid including PCI IDs for one platform to the PCI IDs of another. It's
more clear to deal with them completely separately at the PCI ID macro
level.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1
With IGT no longer using INTEL_VGA_DEVICE(), we can make it kernel
specific and use designated initializers. Ditto for
INTEL_QUANTA_VGA_DEVICE(). Remove the superfluous comments while at it.
Signed-off-by: Jani Nikula
---
IGT INTEL_VGA_DEVICE removal:
https://lore.kernel.org/r/20240902134907.2
There's considerable overlap in i915 and xe PCI ID macros, and (as can
be seen in this series) they get updated out of sync. With i915 display
continuing to use PCI IDs for platforms that i915 core does not support,
but xe does, the duplication will just increase. Just use a single file
for all of
== Series Details ==
Series: drm/i915/display: Fix BMG CCS modifiers (rev4)
URL : https://patchwork.freedesktop.org/series/137958/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15341_full -> Patchwork_137958v4_full
Summary
On 30/08/2024 10:40, Thomas Zimmermann wrote:
Call drm_client_setup() to run the kernel's default client setup
for DRM. Set fbdev_probe in struct drm_driver, so that the client
setup can start the common fbdev client.
The mediatek driver specifies a preferred color mode of 32. As this
is the
== Series Details ==
Series: drm/i915: Use DSB for plane/color management commits
URL : https://patchwork.freedesktop.org/series/138095/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15342 -> Patchwork_138095v1
Summary
On Thu, Aug 22, 2024 at 11:44:48AM +0530, Chaitanya Kumar Borah wrote:
> In case of UHBR rates, we do not need to explicitly enable FEC by writing
> to DP_TP_CTL register.
> For MST use-cases, intel_dp_mst_find_vcpi_slots_for_bpp() takes care of
> setting fec_enable to false. However, it gets overw
== Series Details ==
Series: drm/i915: Use DSB for plane/color management commits
URL : https://patchwork.freedesktop.org/series/138095/
State : warning
== Summary ==
Error: dim checkpatch failed
a5ed980f4c34 drm/i915/dsb: Avoid reads of the DSB buffer for indexed register
writes
f5c46a6ce8d4
== Series Details ==
Series: drm/i915: Use DSB for plane/color management commits
URL : https://patchwork.freedesktop.org/series/138095/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/as
== Series Details ==
Series: Increase fastwake sync pulse count as a quirk (rev3)
URL : https://patchwork.freedesktop.org/series/137524/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15338_full -> Patchwork_137524v3_full
Su
From: Ville Syrjälä
Push regular plane/color management updates to the DSB,
if other constraints allow it.
The first part of the sequence will go as follows:
- CPU will kick off DSB0 immediately
- DSB0 writes double bufferd non-arming registers
- DSB0 evades the vblank
- DSB0 writes double buffe
From: Ville Syrjälä
Pass the 'dsb' all the way down to the color commit hooks so that
we'll be able to update the double buffered color management registers
(eg. CSC) via the DSB.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c| 176 ++
drivers/g
From: Ville Syrjälä
We need to be able to do both MMIO and DSB based pipe/plane
programming. To that end plumb the 'dsb' all way from the top
into the plane commit hooks.
The compiler appears smart enough to combine the branches from
all the back-to-back register writes into a single branch.
So
From: Ville Syrjälä
Extract the code for staging the vblank event for the
flip done interrupt handler. We'll reuse this for DSB
stuff later.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 21 +++--
drivers/gpu/drm/i915/display/intel_crtc.h | 3 +++
From: Ville Syrjälä
Add intel_dsb_wait_vblank_delay() which instructs the DSB
to wait for duration between the undelayed and delayed vblanks.
We'll need this as the DSB can only directly wait for the
undelayed vblank, but we'll need to wait until the delayed
vblank has elapsed as well.
Signed-of
From: Ville Syrjälä
Introduce intel_scanlines_to_usecs() as a counterpart to
intel_usecs_to_scanlines().
We'll have some use for this in DSB code as we want to do
relative scanline waits to evade the delayed vblank, but
unfortunately DSB can't do relative scanline waits (only
absolute). So we'll
From: Ville Syrjälä
Add a function to emit a DSB wait for vblank instruction. This
just waits until the specified number of vblanks.
Note that this triggers on the transcoder's undelayed vblank,
as opposed to the pipe's delayed vblank.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/dis
From: Ville Syrjälä
Add a function to emit the DSB "wait usecs" instruction.
This is just a usleep() for the DSB.
As a lower bound it seems pretty accurate, but the upper bound
seemed oddly relaxed (ie. sometimes I've seen waits that are
quite a bit longer than specified, not sure why).
Signed-
From: Ville Syrjälä
Add a helper for performing vblank evasion on the DSB. DSB based
plane updates will need this to guarantee all the double buffered
arming registers will get programmed atomically within the same
frame.
With VRR we more or less have two vblanks to worry about:
- vmax vblank st
From: Ville Syrjälä
The DSB can signal a programmable interrupt in response to
a specific DSB command getting executed. Hook that up.
For now we'll just use this to signal the completion of the
commit via a vblank event. If, in the future, we'll need to
do other things in response to DSB interru
From: Ville Syrjälä
Once we start using DSB for plane updates we'll need to defer
generating the DSB buffer until the clear color has been
read out. So we need to move at some of the DSB stuff into
commit_tail(). That is perhaps a better place for it anyway
as the ioctl thread can move on immedia
From: Ville Syrjälä
Read out the clear color as soon as fences and the transient
data flush have finished. There is no need to wait for
all the display specific operations that might still be
going on. This could parallelize things a bit more effectively.
Signed-off-by: Ville Syrjälä
---
drive
From: Ville Syrjälä
Reading from the DSB command buffer might be somewhat expensive on
discrete GPUs because the buffer resides in GPU local memory. Avoid
such reads in the indexed register write handling by tracking the
previous instruction in intel_dsb.
TODO: actually measure this
Signed-off-
From: Ville Syrjälä
Use the DSB to perform simple plane/color management commits.
Anything more complicatd (modesets and fastsets) are still
punted to the mmio path.
Also DSB won't be used when any of these are in use:
- scalers (scaler code needs more work)
- VRR (need to figure out a race free
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev5)
URL : https://patchwork.freedesktop.org/series/134383/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15341 -> Patchwork_134383v5
Summ
== Series Details ==
Series: Use VRR timing generator for fixed refresh rate modes (rev5)
URL : https://patchwork.freedesktop.org/series/134383/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/in
On Thu, 29 Aug 2024, Jani Nikula wrote:
> Follow-up to [1].
Thanks for the reviews, pushed to drm-intel-next.
BR,
Jani.
>
> BR,
> Jani.
>
>
> [1] https://lore.kernel.org/r/cover.1723129920.git.jani.nik...@intel.com
>
> Jani Nikula (6):
> drm/i915 & drm/xe: save struct drm_device to drvdata
>
== Series Details ==
Series: drm/i915:Remove unused parameter in marco.
URL : https://patchwork.freedesktop.org/series/138076/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15341 -> Patchwork_138076v1
Summary
---
**F
On Mon, 08 Jul 2024, Animesh Manna wrote:
> As lobf compute config is depends upon delayed vbalnk so moved
> lobf compute config in encoder late config(). Lobf is only
> for edp connector so introduced intel_dp_late_compute_config().
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/
On Mon, 08 Jul 2024, Animesh Manna wrote:
> Panel Replay VSC SDP not getting sent when VRR is enabled
> and W1 and W2 are 0. So Program Set Context Latency in
> TRANS_SET_CONTEXT_LATENCY register to at least a value of 1.
> The same is applicable for PSR1/PSR2 as well.
>
> HSD: 14015406119
>
> v1:
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, September 2, 2024 3:07 PM
> To: Kandpal, Suraj ; intel-
> g...@lists.freedesktop.org
> Cc: Shankar, Uma
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal
On 8/29/2024 8:17 PM, Jani Nikula wrote:
Use to_intel_display() instead of kdev_to_i915() in the HDCP component
API hooks. Avoid further drive-by changes at this point, and just
convert the display pointer to i915, and leave the struct intel_display
conversion for later.
The NULL error checkin
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 29, 2024 8:18 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nikula, Jani ; Vivi, Rodrigo
> ; De Marchi, Lucas ;
> Sousa, Gustavo
> Subject: [PATCH v2 5/6] drm/i91
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 29, 2024 8:18 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nikula, Jani ; Vivi, Rodrigo
> ;
> De Marchi, Lucas ; Sousa, Gustavo
>
> Subject: [PATCH v2 5/6] drm/i91
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, September 2, 2024 3:32 PM
> To: Kandpal, Suraj ; intel-
> g...@lists.freedesktop.org
> Cc: Shankar, Uma
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Mon, 2024-09-02 at 12:37 +0300, Hogander, Joun
On 7/8/2024 8:52 PM, Animesh Manna wrote:
Coonector state is not used in lobf compute config, so removed it.
nitpick: s/coonector/connector and s/removed/remove
Add fixes tag.
With above fixed:
Reviewed-by: Ankit Nautiyal
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/displa
On 7/8/2024 8:52 PM, Animesh Manna wrote:
Panel Replay VSC SDP not getting sent when VRR is enabled
and W1 and W2 are 0. So Program Set Context Latency in
TRANS_SET_CONTEXT_LATENCY register to at least a value of 1.
The same is applicable for PSR1/PSR2 as well.
HSD: 14015406119
v1: Initial ve
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, September 2, 2024 4:44 PM
> To: Kandpal, Suraj ; intel-
> g...@lists.freedesktop.org
> Cc: Shankar, Uma
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Mon, 2024-09-02 at 11:07 +, Kandpal, Suraj
On Mon, 2024-09-02 at 12:37 +0300, Hogander, Jouni wrote:
> On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > entered
> > 2) Allow
On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the
> following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, August 29, 2024 8:18 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nikula, Jani ; Vivi, Rodrigo
> ; De Marchi, Lucas ;
> Sousa, Gustavo
> Subject: [PATCH v2 5/6] drm/i91
On Mon, 2024-09-02 at 10:14 +, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Monday, September 2, 2024 3:32 PM
> > To: Kandpal, Suraj ; intel-
> > g...@lists.freedesktop.org
> > Cc: Shankar, Uma
> > Subject: Re: [PATCH] drm/i915/psr: Implment W
On Mon, 2024-09-02 at 11:07 +, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Monday, September 2, 2024 4:32 PM
> > To: Kandpal, Suraj ; intel-
> > g...@lists.freedesktop.org
> > Cc: Shankar, Uma
> > Subject: Re: [PATCH] drm/i915/psr: Implment W
== Series Details ==
Series: drm/i915/display: Fix BMG CCS modifiers (rev4)
URL : https://patchwork.freedesktop.org/series/137958/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15341 -> Patchwork_137958v4
Summary
---
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, September 2, 2024 4:32 PM
> To: Kandpal, Suraj ; intel-
> g...@lists.freedesktop.org
> Cc: Shankar, Uma
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Mon, 2024-09-02 at 10:14 +, Kandpal, Suraj
== Series Details ==
Series: Introduce DRM device wedged event
URL : https://patchwork.freedesktop.org/series/138069/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15338_full -> Patchwork_138069v1_full
Summary
---
**
On Wed, Aug 28, 2024 at 05:35:45PM +0200, Andi Shyti wrote:
> Hi Sima,
>
> On Wed, Aug 28, 2024 at 03:47:21PM +0200, Daniel Vetter wrote:
> > On Wed, Aug 28, 2024 at 10:20:15AM +0200, Andi Shyti wrote:
> > > Hi Sima,
> > >
> > > first of all, thanks for looking into this series.
> > >
> > > On T
== Series Details ==
Series: Increase fastwake sync pulse count as a quirk (rev3)
URL : https://patchwork.freedesktop.org/series/137524/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15338 -> Patchwork_137524v3
Summary
On Mon, Sep 02, 2024 at 11:27:57AM +0300, Jani Nikula wrote:
> On Thu, 29 Aug 2024, Jani Nikula wrote:
> > The TL;DR is,
> >
> > Reviewed-by: Jani Nikula
> >
> > on the series.
>
> Both pushed to drm-intel-next, thanks for the patches and discussion.
>
> I amended the commit message about clang
On 02/09/24 13:18, Raag Jadav wrote:
> Introduce device wedged event, which will notify userspace of wedged
> (hanged/unusable) state of the DRM device through a uevent. This is
> useful especially in cases where the device is in unrecoverable state
> and requires userspace intervention for recov
On 02/09/24 13:18, Raag Jadav wrote:
This patch looks entirely new from what was sent earlier
so you could send it as a fresh patch.
Thanks,
Aravind,
> From: Himal Prasad Ghimiray
>
> This was previously attempted as xe specific reset uevent but dropped
> in commit 77a0d4d1cea2 ("drm/xe/uapi:
On 02/09/24 13:18, Raag Jadav wrote:
> Now that we have device wedged event supported by DRM core, make use
> of it. With this in place, userspace will be notified of wedged device
> on gt reset failure.
>
> Signed-off-by: Raag Jadav
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 ++
> 1 fil
== Series Details ==
Series: Introduce DRM device wedged event
URL : https://patchwork.freedesktop.org/series/138069/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15338 -> Patchwork_138069v1
Summary
---
**SUCCESS**
On Mon, 02 Sep 2024, Jouni Högander wrote:
> In commit "drm/i915/display: Increase number of fast wake precharge pulses"
> we were increasing Fast Wake sync pulse length to fix problems observed on
> Dell Precision 5490 laptop with AUO panel. Later we have observed this is
> causing problems on ot
== Series Details ==
Series: Introduce DRM device wedged event
URL : https://patchwork.freedesktop.org/series/138069/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Introduce DRM device wedged event
URL : https://patchwork.freedesktop.org/series/138069/
State : warning
== Summary ==
Error: dim checkpatch failed
fe78cca28d79 drm: Introduce device wedged event
-:44: WARNING:STATIC_CONST_CHAR_ARRAY: char * array declaration might
On Mon, 02 Sep 2024, Jouni Högander wrote:
> Currently there is no way to apply quirk on device only if certain panel
> model is installed. This patch implements such mechanism by adding new
> quirk type intel_dpcd_quirk which contains also sink_oui and sink_device_id
> fields and using also them
On Thu, 29 Aug 2024, Jani Nikula wrote:
> The TL;DR is,
>
> Reviewed-by: Jani Nikula
>
> on the series.
Both pushed to drm-intel-next, thanks for the patches and discussion.
I amended the commit message about clang, config options and commit
6863f5643dd7 ("kbuild: allow Clang to find unused sta
Currently VRR timing generator is used only when VRR is enabled by
userspace. From XELPD+, gradually move away from older timing
generator and use VRR timing generator for fixed refresh rate also.
In such a case, Flipline VMin and VMax all are set to the Vtotal of the
mode, which effectively makes
Print vrr.fixed_rr along with other vrr parameters.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
b/drivers/gpu/drm/i915/display/in
Do not program transcoder registers for VRR for the secondary pipe of
the joiner. Remove check to skip VRR for joiner case.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/
As per Bspec:68925: Push enable must be set if not configuring for a
fixed refresh rate (i.e Vmin == Flipline == Vmax is not true).
Signed-off-by: Ankit Nautiyal
Reviewed-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
At the moment PSR/PSR2 are not supported with variable refresh rate.
However it can be supported with fixed refresh rate while running with
VRR timing generator.
Enable PSR for fixed refresh rate when using the VRR timing generator.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/
As per bspec 49268: Disable PSR before disabling VRR.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.
Add support for using VRR Timing generator for HDMI panels.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/inte
Previously, TRANS_VRR_VSYNC was exclusively used for panels with
adaptive-sync SDP support in VRR scenarios. However, to drive fixed refresh
rates using the VRR Timing generator, we now need to program
TRANS_VRR_VSYNC regardless of adaptive sync SDP support. Therefore, let's
remove the adaptive syn
While running with fixed refresh rate and VRR timing generator set FAVT
mode (Fixed Vtotal) in DP Adaptive Sync SDP to intimate the panel
about Fixed refresh rate.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 ins
MSA Ignore Timing PAR enable is set in the DP sink when we enable variable
refresh rate. When using VRR timing generator for fixed refresh rate
we do not want to ignore the mode timings, as the refresh rate is still
fixed. Modify the checks to enable MSA Ignore Timing PAR only when not
in fixed_rr
Add fixed_rr member to struct vrr to represent the case where a
fixed refresh rate with VRR timing generator is required.
v2: Move get_config change where vrr.fixed is actually set. (Mitul)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
drivers/gp
Currently we support Adaptive sync operation mode with dynamic frame
rate, but instead the operation mode with fixed rate is set.
This was initially set correctly in the earlier version of changes but
later got changed, while defining a macro for the same.
Fixes: a5bd5991cb8a ("drm/i915/display: C
Even though the VRR timing generator (TG) is primarily used for
variable refresh rates, it can be used for fixed refresh rates as
well. For a fixed refresh rate the Flip Line and Vmax must be equal
(TRANS_VRR_FLIPLINE = TRANS_VRR_VMAX). Beyond that, there are some
dependencies between the VRR timin
Currently we do not support VRR with HDMI so skip vrr compute
config step for DP with HDMI sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/
The parameter dev_priv is actually not used in macro PORT_ALPM_CTL
and PORT_ALPM_LFPS_CTL,so remove it to simplify the code.
Signed-off-by: He Lugang
---
drivers/gpu/drm/i915/display/intel_alpm.c | 4 ++--
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/display/int
On Mon, 02 Sep 2024, Raag Jadav wrote:
> Introduce device wedged event, which will notify userspace of wedged
> (hanged/unusable) state of the DRM device through a uevent. This is
> useful especially in cases where the device is in unrecoverable state
> and requires userspace intervention for reco
== Series Details ==
Series: Increase fastwake sync pulse count as a quirk (rev3)
URL : https://patchwork.freedesktop.org/series/137524/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15338 -> Patchwork_137524v3
Summary
Let I915_FORMAT_MOD_4_TILED_BMG_CCS show up as supported modifier
Fixes: 97c6efb36497 ("drm/i915/display: Plane capability for 64k phys
alignment")
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/dr
== Series Details ==
Series: Increase fastwake sync pulse count as a quirk (rev3)
URL : https://patchwork.freedesktop.org/series/137524/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/as
Now that we have device wedged event supported by DRM core, make use
of it. With this in place, userspace will be notified of wedged device
on gt reset failure.
Signed-off-by: Raag Jadav
---
drivers/gpu/drm/i915/gt/intel_reset.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/d
From: Himal Prasad Ghimiray
This was previously attempted as xe specific reset uevent but dropped
in commit 77a0d4d1cea2 ("drm/xe/uapi: Remove reset uevent for now")
as part of refactoring.
Now that we have device wedged event supported by DRM core, make use
of it. With this in place userspace w
Introduce device wedged event, which will notify userspace of wedged
(hanged/unusable) state of the DRM device through a uevent. This is
useful especially in cases where the device is in unrecoverable state
and requires userspace intervention for recovery.
Purpose of this implementation is to be v
This series introduces device wedged event in DRM subsystem and uses
it in xe and i915 drivers. Detailed description in commit message.
This was earlier attempted as xe specific uevent in v1 and v2.
https://patchwork.freedesktop.org/series/136909/
v2: Change authorship to Himal (Aravind)
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