Existing userspace assumes there's no gaps card’s, but I see cards
are not continues, after running “gta@core_hotunplug I am not seeing card0,
hence test is failing.
Test result before this changes:
root@DUT1523LNL:/usr/local/libexec/igt-gpu-tools#
root@DUT1523LNL:/usr/local/libexec/igt-gpu-tools#
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 13/14] drm/i915/dp_mst: Ensure link parameters are up-to-
> date for a disabled link
>
> As explained in the previous patch, th
> -Original Message-
> From: Kandpal, Suraj
> Sent: Monday, July 22, 2024 12:15 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Kandpal, Suraj
>
> Subject: [PATCH 0/2] Fix null pointer error in HDCP capability check
>
> During suspend
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, July 24, 2024 4:50 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 07/14] drm/i915/dp: Add a separate function to reduce the
> link parameters
>
> On Wed, Jul 24, 2024 at 07:55:03AM +0300, Murt
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, July 24, 2024 4:46 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 06/14] drm/i915/dp: Send only a single modeset-retry
> uevent for a commit
>
> On Wed, Jul 24, 2024 at 07:29:33AM +0300, Murth
> -Original Message-
> From: Kandpal, Suraj
> Sent: Wednesday, July 24, 2024 10:32 PM
> To: Nemesa Garg ; intel...@lists.freedesktop.org
> Cc: Heikkila, Juha-pekka ; Shankar, Uma
> ; Garg, Nemesa
> Subject: RE: [PATCH] drm/i915/display: Workaround for odd panning for
> planar yuv
>
>
== Series Details ==
Series: drm/i915: Fix possible int overflow in skl_ddi_calculate_wrpll()
URL : https://patchwork.freedesktop.org/series/136455/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15126 -> Patchwork_136455v1
On the off chance that clock value ends up being too high (by means
of skl_ddi_calculate_wrpll() having benn called with big enough
value of crtc_state->port_clock * 1000), one possible consequence
may be that the result will not be able to fit into signed int.
Fix this, albeit unlikely, issue by
On Wed, Jul 24, 2024 at 07:03:51PM +0300, Jani Nikula wrote:
> [...]
> Imre, I'm looking at the warnings in intel_tc.c in general, and
> adlp_tc_phy_connect() in particular, and I think this is too hard to
> parse:
>
> if (!adlp_tc_phy_take_ownership(tc, true) &&
> !drm_WARN_ON(&i9
On Mon, Jul 15, 2024 at 08:35:43PM +0200, Francesco Poli wrote:
> Hi all,
> on a laptop where I installed Debian testing some 6 months ago,
> I noticed that the logs are continuously flooded with call traces
> like the attached snippet (taken from /var/log/kern.log ).
>
> It seems to me that it al
> -Original Message-
> From: Intel-xe On Behalf Of Suraj
> Kandpal
> Sent: Monday, July 22, 2024 12:15 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Kandpal, Suraj
>
> Subject: [PATCH 3/3] drm/xe/hdcp: Check GSC structure validity
>
> -Original Message-
> From: Intel-gfx On Behalf Of Suraj
> Kandpal
> Sent: Monday, July 22, 2024 12:15 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Kandpal, Suraj
>
> Subject: [PATCH 2/3] drm/i915/hdcp: Add encoder check in
> hdcp2
> -Original Message-
> From: Intel-xe On Behalf Of Suraj
> Kandpal
> Sent: Monday, July 22, 2024 12:15 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Kandpal, Suraj
>
> Subject: [PATCH 1/3] drm/i915/hdcp: Add encoder check in
> intel_
== Series Details ==
Series: drm/i915/dp: Clear VSC SDP during post ddi disable routine (rev2)
URL : https://patchwork.freedesktop.org/series/136369/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15125 -> Patchwork_136369v2
We are seeing several instances where the RPe, which can be altered by
pcode dynamically, is causing subtests to fail randomly. Instead of relying
on it, we can use a mid frequency value for these subtests and avoid these
failures.
Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2262
L
== Series Details ==
Series: drm/i915/dp_mst: Fix MST state after a sink reset
URL : https://patchwork.freedesktop.org/series/136443/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15124 -> Patchwork_136443v1
Summary
---
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, July 24, 2024 4:57 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 09/14] drm/i915/dp_mst: Reduce the link parameters in
> BW order after LT failures
>
> On Wed, Jul 24, 2024 at 09:43:55AM +
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, July 24, 2024 5:03 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 14/14] drm/i915/dp_mst: Enable LT fallback between
> UHBR/non-UHBR link rates
>
> On Wed, Jul 24, 2024 at 11:52:14AM +0300,
Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable
routine i.e with the variable of enable as false. This is to avoid
an infoframes.enable mismatch issue which is caused when pipe is
connected to eDp which has psr then connected to DPMST. In this case
eDp's post ddi disable ro
On Wed, Jul 24, 2024 at 07:21:53PM +0300, Jani Nikula wrote:
> On Wed, 24 Jul 2024, Imre Deak wrote:
> > In some cases the sink can reset itself after it was configured into MST
> > mode, without the driver noticing the disconnected state. For instance
> > the reset may happen in the middle of a m
On Wed, 24 Jul 2024, Imre Deak wrote:
> In some cases the sink can reset itself after it was configured into MST
> mode, without the driver noticing the disconnected state. For instance
> the reset may happen in the middle of a modeset, or the (long) HPD pulse
> generated may be not long enough fo
On Mon, Jul 22, 2024 at 2:07 PM Lucas De Marchi
wrote:
>
> If a pmu is unregistered while there's an active event, perf will still
> access the pmu via event->pmu, even after the event is destroyed. This
> makes it difficult for drivers like i915 that take a reference on the
> device when the even
In some cases the sink can reset itself after it was configured into MST
mode, without the driver noticing the disconnected state. For instance
the reset may happen in the middle of a modeset, or the (long) HPD pulse
generated may be not long enough for the encoder detect handler to
observe the HPD
On Mon, 15 Jul 2024, Francesco Poli wrote:
> Hi all,
> on a laptop where I installed Debian testing some 6 months ago,
> I noticed that the logs are continuously flooded with call traces
> like the attached snippet (taken from /var/log/kern.log ).
>
> It seems to me that it also used to happen wit
On Mon, 15 Jul 2024, Francesco Poli wrote:
> Hi all,
> on a laptop where I installed Debian testing some 6 months ago,
> I noticed that the logs are continuously flooded with call traces
> like the attached snippet (taken from /var/log/kern.log ).
>
> It seems to me that it also used to happen wit
== Series Details ==
Series: drm/i915/display: Workaround for odd panning for planar yuv
URL : https://patchwork.freedesktop.org/series/136416/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15123_full -> Patchwork_136416v1_full
=
On Wed, Jul 24, 2024 at 02:41:05PM GMT, Peter Zijlstra wrote:
On Tue, Jul 23, 2024 at 10:30:08AM -0500, Lucas De Marchi wrote:
On Tue, Jul 23, 2024 at 09:03:25AM GMT, Tvrtko Ursulin wrote:
>
> On 22/07/2024 22:06, Lucas De Marchi wrote:
> > Instead of calling perf_pmu_unregister() when unbinding
== Series Details ==
Series: drm/i915/gt: Stop poisoning the idle kernel context alone when waking up
URL : https://patchwork.freedesktop.org/series/136433/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15124 -> Patchwork_136433v1
==
On Wed, 24 Jul 2024, "Nautiyal, Ankit K" wrote:
> On 7/23/2024 9:58 AM, Suraj Kandpal wrote:
>> Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable
>> routine i.e with the variable of enable as false. This is to avoid
>> an infoframes.enable mismatch issue which is caused when
== Series Details ==
Series: drm/i915/gt: Stop poisoning the idle kernel context alone when waking up
URL : https://patchwork.freedesktop.org/series/136433/
State : warning
== Summary ==
Error: dim checkpatch failed
30c921464da6 drm/i915/gt: Stop poisoning the idle kernel context alone when
w
On Tue, 23 Jul 2024, Arunpravin Paneer Selvam
wrote:
> - Add a new start parameter in trim function to specify exact
> address from where to start the trimming. This would help us
> in situations like if drivers would like to do address alignment
> for specific requirements.
>
> - Add a new
== Series Details ==
Series: spi: add driver for Intel discrete graphics (rev2)
URL : https://patchwork.freedesktop.org/series/131763/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/131763/revisions/2/mbox/ not
applied
Applying: spi: add driver fo
From: Chris Wilson
The kernel context was poisoned on wakeup to simulate how the driver
would cope with bad HW that caused corruption of any context that was
still resident during power loss, see commit 1d0e2c9359fe ("drm/i915/gt:
Always poison the kernel_context image before unparking"). However
Enable access to internal spi on DGFX with GSC/CSC devices
via a child device.
The spi child device is exposed via auxiliary bus.
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_device.c | 3 ++
drivers/gpu/drm/xe/xe_device_types.h |
From: Tomas Winkler
Add the dGFX spi region map and convey it via auxiliary device
to the spi child device.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/spi/intel_spi.c | 8
1 file changed, 8 insertions(
From: Tomas Winkler
Implement mtd read, erase, and write handlers.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-o
Check SPI access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 5
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +---
drivers/gpu/drm/xe/xe_spi.c | 33 ++
From: Tomas Winkler
Enable access to internal spi on DGFX devices via a child device.
The spi child device is exposed via auxiliary bus.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/Makefile| 4 ++
drive
Check SPI access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/spi/intel_spi.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/in
GSC SPI HW errors on quad access overlapping 1K border.
Align 64bit read and write to avoid readq/writeq over 1K border.
Signed-off-by: Alexander Usyskin
---
drivers/spi/spi-intel-dg.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/spi/spi-intel-
Enable runtime PM in spi driver to notify graphics driver that
whole card should be kept awake while spi operations are
performed through this driver.
CC: Lucas De Marchi
Signed-off-by: Alexander Usyskin
---
drivers/spi/spi-intel-dg.c | 44 ++
1 file changed,
From: Tomas Winkler
Register the on-die spi device with the mtd subsystem.
Refcount spi object on _get and _put mtd callbacks.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/spi/spi-intel-dg.c | 111
From: Tomas Winkler
Implement spi_read(), spi_erase() and spi_write() functions.
CC: Lucas De Marchi
CC: Rodrigo Vivi
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-off-by: Alexander Usyskin
---
drivers/spi/spi-intel-dg.c | 199 +
1 fil
From: Tomas Winkler
In intel-dg spi, there is no access to the spi controller,
the information is extracted from the descriptor region.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/spi/spi-intel-dg.c | 190 +++
Add auxiliary driver for intel discrete graphics
on-die spi device.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
MAINTAINERS | 7 ++
drivers/spi/Kconfig | 11 +++
drivers/spi/Makefile |
Add driver for access to Intel discrete graphics card
internal SPI device.
Expose device on auxiliary bus by i915 and Xe drivers and
provide spi driver to register this device with MTD framework.
This is a rewrite of "drm/i915/spi: spi access for discrete graphics"
series with connection to the Xe
On Tue, Jul 23, 2024 at 10:30:08AM -0500, Lucas De Marchi wrote:
> On Tue, Jul 23, 2024 at 09:03:25AM GMT, Tvrtko Ursulin wrote:
> >
> > On 22/07/2024 22:06, Lucas De Marchi wrote:
> > > Instead of calling perf_pmu_unregister() when unbinding, defer that to
> > > the destruction of i915 object. Si
== Series Details ==
Series: drm/i915/display: Workaround for odd panning for planar yuv
URL : https://patchwork.freedesktop.org/series/136416/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15123 -> Patchwork_136416v1
Summa
On Wed, Jul 24, 2024 at 11:52:14AM +0300, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Imre
> > Deak
> > Sent: Monday, July 22, 2024 10:25 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH 14/14] drm/i915/dp_mst: Enable LT fallback betwee
Underrun/corruption issue is seen for NV12 format
for odd panning on LNL due to hardware bug.
Disable the format.
HSD: 16024459452
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/di
On Wed, Jul 24, 2024 at 09:43:55AM +0300, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Imre
> > Deak
> > Sent: Monday, July 22, 2024 10:25 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH 09/14] drm/i915/dp_mst: Reduce the link parameter
Am 24.07.24 um 11:37 schrieb Matthew Auld:
On 24/07/2024 02:35, Marek Olšák wrote:
The reason is that our DCC requires 768K alignment in some cases. I
haven't read this patch series, but one way to do that is to align to
256K, overallocate by 512K, and then not use either 0, 256K, or 512K
at t
On Wed, Jul 24, 2024 at 07:55:03AM +0300, Murthy, Arun R wrote:
> > -Original Message-
> > From: Intel-gfx On Behalf Of Imre
> > Deak
> > Sent: Monday, July 22, 2024 10:25 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH 07/14] drm/i915/dp: Add a separate function to reduce t
On Wed, Jul 24, 2024 at 07:29:33AM +0300, Murthy, Arun R wrote:
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Imre
> > Deak
> > Sent: Monday, July 22, 2024 10:25 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH 06/14] drm/i915/dp: Send only a single modeset-retry
On Mon, 22 Jul 2024, Colin Ian King wrote:
> Don't populate the read-only array bw_gbps on the stack at run time,
> instead make it static const.
>
> Signed-off-by: Colin Ian King
Pushed to drm-intel-next, thanks for the patch.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
On 23/07/2024 14:25, Arunpravin Paneer Selvam wrote:
- Add a new start parameter in trim function to specify exact
address from where to start the trimming. This would help us
in situations like if drivers would like to do address alignment
for specific requirements.
- Add a new flag DR
On 24/07/2024 02:35, Marek Olšák wrote:
The reason is that our DCC requires 768K alignment in some cases. I
haven't read this patch series, but one way to do that is to align to
256K, overallocate by 512K, and then not use either 0, 256K, or 512K at
the beginning to get to 768K alignment.
Ah,
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 14/14] drm/i915/dp_mst: Enable LT fallback between
> UHBR/non-UHBR link rates
>
> Enable switching between UHBR and non-UHBR li
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 12/14] drm/i915/dp_mst: Reprobe the MST topology after a
> link parameter change
>
> The MST link BW reported by branch devices
On 12-07-2024 17:53, Raag Jadav wrote:
Add hwmon support for fan1_input attribute, which will expose fan speed
in RPM. With this in place we can monitor fan speed using lm-sensors tool.
$ sensors
i915-pci-0300
Adapter: PCI adapter
in0: 653.00 mV
fan1:3833 RPM
power1:
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 11/14] drm/i915/dp_mst: Queue modeset-retry after a
> failed payload BW allocation
>
> If the MST payload allocation failed, en
On 23/07/2024 16:30, Lucas De Marchi wrote:
On Tue, Jul 23, 2024 at 09:03:25AM GMT, Tvrtko Ursulin wrote:
On 22/07/2024 22:06, Lucas De Marchi wrote:
Instead of calling perf_pmu_unregister() when unbinding, defer that to
the destruction of i915 object. Since perf itself holds a reference in
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