> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 10/14] drm/i915/dp_mst: Configure MST after the link
> parameters are reset
>
> The MST topology probing depends on the maximum
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 09/14] drm/i915/dp_mst: Reduce the link parameters in BW
> order after LT failures
>
> On MST links - at least for some MST bra
On 7/23/2024 9:58 AM, Suraj Kandpal wrote:
Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable
routine i.e with the variable of enable as false. This is to avoid
an infoframes.enable mismatch issue which is caused when pipe is
connected to eDp which has psr then connected t
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 07/14] drm/i915/dp: Add a separate function to reduce the link
> parameters
>
> A follow-up patch will add an alternative way to r
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 06/14] drm/i915/dp: Send only a single modeset-retry uevent
> for a commit
>
> There are multiple failure cases a modeset-retry
On 7/5/2024 3:13 PM, Nemesa Garg wrote:
In panel fitter/pipe scaler scenario the pch_pfit configuration
currently takes place before we account for bigjoiner.
So once the calculation for bigjoiner is done, proper values
of width and height can be used for panel fitting.
I think this seems to
The reason is that our DCC requires 768K alignment in some cases. I haven't
read this patch series, but one way to do that is to align to 256K,
overallocate by 512K, and then not use either 0, 256K, or 512K at the
beginning to get to 768K alignment.
Marek
On Tue, Jul 23, 2024, 11:04 Matthew Auld
+1. It would help to have an explicit CCS modifier should an unforeseen corner
case arise.
Also, as Ken mentioned, CPU mapped accesses require that compressed images be
resolved beforehand. By having both a 4_TILED modifier and a 4_TILED_XE2_CCS
modifier, applications can avoid performance pena
== Series Details ==
Series: series starting with [v7,1/2] drm/buddy: Add start address support to
trim function
URL : https://patchwork.freedesktop.org/series/136388/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15117_full -> Patchwork_136388v1_full
Hello Anna-Maria,
Hope you are doing well. I am Chaitanya from the linux graphics team in Intel.
This mail is regarding a regression we are seeing in our CI runs[1] on
linux-next repository.
Since the version next-20240722 [2], we are seeing the following regression
```
On Tue, Jul 23, 2024 at 09:03:25AM GMT, Tvrtko Ursulin wrote:
On 22/07/2024 22:06, Lucas De Marchi wrote:
Instead of calling perf_pmu_unregister() when unbinding, defer that to
the destruction of i915 object. Since perf itself holds a reference in
the event, this only happens when all events ar
On 23/07/2024 14:43, Paneer Selvam, Arunpravin wrote:
Hi Matthew,
Can we push this version for now as we need to mainline the DCC changes
ASAP,
while we continue our discussion and proceed to implement the permanent
solution
for address alignment?
Yeah, we can always merge now and circle ba
On 7/23/2024 3:53 PM, Raag Jadav wrote:
On Mon, Jul 22, 2024 at 04:20:51PM +0530, Riana Tauro wrote:
Hi Raag
On 7/12/2024 5:53 PM, Raag Jadav wrote:
Add hwmon support for fan1_input attribute, which will expose fan speed
in RPM. With this in place we can monitor fan speed using lm-sensors t
== Series Details ==
Series: series starting with [v7,1/2] drm/buddy: Add start address support to
trim function
URL : https://patchwork.freedesktop.org/series/136388/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15117 -> Patchwork_136388v1
==
== Series Details ==
Series: series starting with [v7,1/2] drm/buddy: Add start address support to
trim function
URL : https://patchwork.freedesktop.org/series/136388/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked se
Hi Matthew,
Can we push this version for now as we need to mainline the DCC changes
ASAP,
while we continue our discussion and proceed to implement the permanent
solution
for address alignment?
Thanks,
Arun.
On 7/23/2024 6:55 PM, Arunpravin Paneer Selvam wrote:
- Add a new start parameter i
- Add a new start parameter in trim function to specify exact
address from where to start the trimming. This would help us
in situations like if drivers would like to do address alignment
for specific requirements.
- Add a new flag DRM_BUDDY_TRIM_DISABLE. Drivers can use this
flag to disab
Add address alignment support to the DCC VRAM buffers.
v2:
- adjust size based on the max_texture_channel_caches values
only for GFX12 DCC buffers.
- used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only
for DCC buffers.
- roundup non power of two DCC buffer adjusted size to nea
> -Original Message-
> From: Deak, Imre
> Sent: Tuesday, July 23, 2024 5:30 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 05/14] drm/i915/dp: Initialize the link parameters during
> HW readout
>
> On Tue, Jul 23, 2024 at 11:34:58AM +0300, Kandpal,
> -Original Message-
> From: Deak, Imre
> Sent: Tuesday, July 23, 2024 5:26 PM
> To: Kandpal, Suraj
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 04/14] drm/i915/ddi: For an active output call the DP
> encoder sync_state() only for DP
>
> On Tue, Jul 23, 2024 at 11:28:33
On Tue, Jul 23, 2024 at 11:34:58AM +0300, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Imre
> > Deak
> > Sent: Monday, July 22, 2024 10:25 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH 05/14] drm/i915/dp: Initialize the link parameter
On Tue, Jul 23, 2024 at 11:28:33AM +0300, Kandpal, Suraj wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Imre
> > Deak
> > Sent: Monday, July 22, 2024 10:25 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH 04/14] drm/i915/ddi: For an active output call th
== Series Details ==
Series: CCS static load balance
URL : https://patchwork.freedesktop.org/series/136381/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
CC [M] drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.o
dr
Add documentation for how to set the static CCS load balancing.
Signed-off-by: Andi Shyti
---
Documentation/gpu/i915.rst | 3 ++
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 56 +
2 files changed, 59 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/
Create the 'ccs_mode' file under
/sys/class/drm/cardX/gt/gt0/ccs_mode
This file allows the user to read and set the current CCS mode.
- Reading: The user can read the current CCS mode, which can be
1, 2, or 4. This value is derived from the current engine
mask.
- Writing: The user can s
Until now, we have only set CCS mode balancing to 1, which means
that only one compute engine is exposed to the user. The stream
of compute commands submitted to that engine is then shared among
all the dedicated execution units.
This is done by calling the 'intel_gt_apply_ccs_mode(); function.
W
Engines and their properties are exposed in:
/sys/class/drm/cardX/engine/
These files are cleaned up when the driver is removed. However,
when the presence of engines starts changing dynamically, we need
a function to clean up the existing ones.
Store the engine-related objects (kobj and kobj_de
Store the CCS mode value in the intel_gt->ccs structure to make
it available for future instances that may need to change its
value.
Name it mode_reg_val because it holds the value that will
be written into the CCS_MODE register, determining the CCS
balancing and, consequently, the number of engin
In anticipation of upcoming patches, it is more convenient to
move the CCS mode mask creation to the intel_ccs_mode.c file,
which serves as a placeholder for all CCS engine settings.
No functional changes intended.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 50 -
Implement a sysfs interface to show the number of available CCS
slices. The displayed number does not take into account the CCS
balancing mode.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 23 +
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 1 +
Hi,
This patch series introduces static load balancing for GPUs with
multiple compute engines. It's a lengthy series, and some
challenging aspects still need to be resolved.
I have tried to split the work as much as possible to facilitate
the review process.
To summarize, in patches 1 to 7, no f
For the upcoming changes we need a cleaner way to build the list
of uabi engines.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 -
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i9
drm/i915/gt: Rename "cslises" variable to clarify its purpose
The "cslises" variable stores the mask of the CCS engines after
calculating the fused ones and before setting the CCS mode.
Since it represents a mask and not the number of CCS slices,
rename it to reflect its actual purpose to avoid c
On Mon, Jul 22, 2024 at 04:20:51PM +0530, Riana Tauro wrote:
> Hi Raag
>
> On 7/12/2024 5:53 PM, Raag Jadav wrote:
> > Add hwmon support for fan1_input attribute, which will expose fan speed
> > in RPM. With this in place we can monitor fan speed using lm-sensors tool.
> >
> > $ sensors
> > i915-
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 08/14] drm/i915/dp: Add helpers to set link training mode, BW
> parameters
>
> Add helpers to set the link mode and BW paramete
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 07/14] drm/i915/dp: Add a separate function to reduce the link
> parameters
>
> A follow-up patch will add an alternative way t
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 05/14] drm/i915/dp: Initialize the link parameters during
> HW readout
>
> Initialize the DP link parameters during HW readout.
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 04/14] drm/i915/ddi: For an active output call the DP
> encoder sync_state() only for DP
>
> If the DDI encoder output is enabl
On 22/07/2024 22:06, Lucas De Marchi wrote:
Instead of calling perf_pmu_unregister() when unbinding, defer that to
the destruction of i915 object. Since perf itself holds a reference in
the event, this only happens when all events are gone, which guarantees
i915 is not unregistering the pmu wit
On 22/07/2024 22:06, Lucas De Marchi wrote:
There's no need to free the resources during unbind. Since perf events
may still access them due to open events, it's safer to free them when
dropping the last i915 reference.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pmu.c | 21
On 22/07/2024 22:06, Lucas De Marchi wrote:
There's no reason to hardcode checking for integrated graphics on a
specific pci slot. That information is already available per platform an
can be checked with IS_DGFX().
Hmm probably reason was this, added is_igp:
commit 05488673a4d41383f9dd537f2
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