== Series Details ==
Series: Add HDMI PLL Algorithm for SNPS/C10PHY
URL : https://patchwork.freedesktop.org/series/135397/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15000 -> Patchwork_135397v1
Summary
---
**SUCCE
== Series Details ==
Series: Add HDMI PLL Algorithm for SNPS/C10PHY
URL : https://patchwork.freedesktop.org/series/135397/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./arch/x86/include/asm/bitops.h:1
== Series Details ==
Series: Add HDMI PLL Algorithm for SNPS/C10PHY
URL : https://patchwork.freedesktop.org/series/135397/
State : warning
== Summary ==
Error: dim checkpatch failed
3e40cbc4f650 drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for
DG2
-:32: WARNING:FILE_PATH_CHAN
Had formatting issues with the first review, sending it again for clarity.
On 6/26/2024 01:56, Gustavo Sousa wrote:
Starting with Xe_LPDP, support for Type-C connections is provided by
PICA and programming PORT_TX_DFLEXDPMLE1(*) registers is not applicable
anymore. Those registers don't even exi
On 6/26/2024 01:56, Gustavo Sousa wrote:
Starting with Xe_LPDP, support for Type-C connections is provided by
PICA and programming PORT_TX_DFLEXDPMLE1(*) registers is not applicable
anymore. Those registers don't even exist in recent display IPs. As
such, skip programming them.
Bspec: 65750, 65
Include the intel_pll_algorithm for xe driver.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/xe/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 478acc94a71c..30b63c2eadd0 100644
--- a/drivers/gpu/drm/xe/Makefile
+++
Add C10 register bits to be used for computing HDMI PLLs with
algorithm.
Signed-off-by: Ankit Nautiyal
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24 +++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
b/drivers/gpu/drm/i
Add support for computing C10 HDMI PLLS using the HDMI PLL algorithm.
Try C10 HDMI tables computed with the algorithm, before using the
consolidated tables.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 15 +
.../drm/i915/display/intel_pll_algorithm.c|
Try SNPS_PHY HDMI tables computed using the algorithm, before using
consolidated tables.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 20 ---
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_snp
Add helper _intel_phy_compute_hdmi_tmds_pll to calculate the necessary
parameters for configuring the HDMI PLL for SNPS MPLLB and C10 PHY.
The pll parameters are computed for desired pixel clock, curve data
and other inputs used for interpolation and finally stored in the
pll_state. Bspec:54032
C
The HDMI PLL programming involves pre-calculated values for specific
frequencies and an algorithm to compute values for other frequencies.
While the algorithm itself wasn't part of the driver, tables were
added based on it for known modes.
Some HDMI modes were pruned due to lack of support (for ex
== Series Details ==
Series: drm/i915/dsb: Use chained DSBs for LUT programming
URL : https://patchwork.freedesktop.org/series/135316/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14996_full -> Patchwork_135316v1_full
Summ
== Series Details ==
Series: drm/i915: Skip programming FIA link enable bits for MTL+
URL : https://patchwork.freedesktop.org/series/135387/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15000 -> Patchwork_135387v1
Summary
Starting with Xe_LPDP, support for Type-C connections is provided by
PICA and programming PORT_TX_DFLEXDPMLE1(*) registers is not applicable
anymore. Those registers don't even exist in recent display IPs. As
such, skip programming them.
Bspec: 65750, 65448
Signed-off-by: Gustavo Sousa
---
drive
Quoting Mika Kahola (2024-06-25 08:18:40-03:00)
>From: Imre Deak
>
>For MTL+ platforms we use PICA chips for Type-C support and
>hence mg programming is not needed.
>
>Fixes issue with drm warn of TC port not being in legacy mode.
>
>Signed-off-by: Mika Kahola
>Signed-off-by: Imre Deak
Reviewed
On Tue, Jun 25, 2024 at 02:05:39PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Enable CCS+10bpc and CCS+async flips
> URL : https://patchwork.freedesktop.org/series/135306/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_14995_full -> Patchwork
On Wed, Jun 19, 2024 at 03:01:03PM +0300, Imre Deak wrote:
> On Wed, Jun 19, 2024 at 01:10:09PM +0300, Jani Nikula wrote:
> > On Fri, 14 Jun 2024, Imre Deak wrote:
> > > Add helpers to convert between x16 fixed point and integer/fraction
> > > values. Also add the format/argument macros required t
== Series Details ==
Series: drm/i915/dsb: Use chained DSBs for LUT programming (rev2)
URL : https://patchwork.freedesktop.org/series/135316/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14998 -> Patchwork_135316v2
Summary
== Series Details ==
Series: drm/i915/dsb: Use chained DSBs for LUT programming (rev2)
URL : https://patchwork.freedesktop.org/series/135316/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/inclu
== Series Details ==
Series: drm/i915/dsb: Use chained DSBs for LUT programming (rev2)
URL : https://patchwork.freedesktop.org/series/135316/
State : warning
== Summary ==
Error: dim checkpatch failed
1b4e1fa4926a drm/i915: Calculate vblank delay more accurately
807da0774682 drm/i915: Make vrr
From: Ville Syrjälä
Enable all DSB error/fault interrupts so that we can see if
anything goes terribly wrong.
v2: Pass intel_display to DISPLAY_VER() (Jani)
Drop extra '/' from drm_err() for consistency
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_displ
== Series Details ==
Series: drm/i915/display: For MTL+ platforms skip mg dp programming
URL : https://patchwork.freedesktop.org/series/135351/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14997 -> Patchwork_135351v1
Summa
From: Imre Deak
For MTL+ platforms we use PICA chips for Type-C support and
hence mg programming is not needed.
Fixes issue with drm warn of TC port not being in legacy mode.
Signed-off-by: Mika Kahola
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
1 file chan
On 19/06/2024 15:31, Matthew Auld wrote:
On BMG-G21 we need to disable fbc due to complications around the WA.
Signed-off-by: Matthew Auld
Cc: Jonathan Cavitt
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Vinod Govindapillai
Cc: intel-gfx@lists.freedesktop.org
Can this be merged via drm-xe-next? T
On Mon, 24 Jun 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Enable all DSB error/fault interrupts so that we can see if
> anything goes terribly wrong.
>
> Signed-off-by: Ville Syrjälä
> ---
> .../gpu/drm/i915/display/intel_display_irq.c | 17 ++
> drivers/gpu/drm/i915/display/inte
On Mon, 2024-06-24 at 05:56 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Wednesday, June 19, 2024 11:51 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Kahola, Mika
> > ; Hogander, Jouni
> > Subject: [PATCH v9 00/11] Pan
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