> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Monday, June 10, 2024 8:18 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K
> Subject: [PATCH v15 0/9] Implement CMRR Support
>
> CMRR is a display feature that uses adaptive sync framework to v
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Monday, June 10, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K
> Subject: [PATCH v16 2/9] drm/i915: Separate VRR related register definitions
>
> Move VRR related register definition
== Series Details ==
Series: drm/i915/dp_mst: Enable link training fallback (rev5)
URL : https://patchwork.freedesktop.org/series/133624/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14913 -> Patchwork_133624v5
Summary
---
On Fri, Jun 07, 2024 at 06:25:40PM +0300, Jani Nikula wrote:
> None of these are used. The parametrized register macros all depend on
> the pipe/plane A offset macros alone. Remove the unused ones.
>
> v2: Rebase
Reviewed-by: Rodrigo Vivi
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/dr
On Fri, Jun 07, 2024 at 06:25:39PM +0300, Jani Nikula wrote:
> Some plane B/C specific bits were left next to the unused _DSPBCNTR
> macro. Move them next to the DSPCNTR() macro.
Reviewed-by: Rodrigo Vivi
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/i9xx_plane_regs.h |
== Series Details ==
Series: drm/i915/dp_mst: Enable link training fallback (rev5)
URL : https://patchwork.freedesktop.org/series/133624/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/a
== Series Details ==
Series: drm/i915/dp_mst: Enable link training fallback (rev5)
URL : https://patchwork.freedesktop.org/series/133624/
State : warning
== Summary ==
Error: dim checkpatch failed
6b81ae31508b drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs
c0a07f914e22 drm/i
Recheck the link state after a passing link training, with a 2 sec delay
to account for cases where the link goes bad following the link training
and the sink doesn't report this via an HPD IRQ.
The delayed work added here will be also used by a later patch after a
failed link training to try to r
== Series Details ==
Series: drm/i915/dp_mst: Enable link training fallback (rev4)
URL : https://patchwork.freedesktop.org/series/133624/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14912 -> Patchwork_133624v4
Summary
---
== Series Details ==
Series: drm/i915/dp_mst: Enable link training fallback (rev4)
URL : https://patchwork.freedesktop.org/series/133624/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/a
== Series Details ==
Series: drm/i915/dp_mst: Enable link training fallback (rev4)
URL : https://patchwork.freedesktop.org/series/133624/
State : warning
== Summary ==
Error: dim checkpatch failed
b20509cd82df drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs
6ec52f74625f drm/i
Simplify things by retraining a DP link if a bad link is detected in the
HPD IRQ handler from the encoder's check link state work, similarly to
how this is done after a modeset link training failure.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +++
1 file ch
Add connector debugfs entries to force the link rate/lane count to be
used by a link training afterwards. These settings will be clamped to
the supported, i.e. the source's and sink's common rate/lane count.
After forcing the link rate/lane count reset the link training
parameters and for a non-au
Add connector debugfs entries to get the maximum link rate and lane
count.
v2: Lock connection_mutex only for the required intel_dp state. (Ville)
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_dp_link_training.c | 44 +++
1 file changed, 44 insertion
From: Imre Deak
The next patch adds sending a modeset-retry uevent after a link training
failure to all MST connectors on link. This requires the atomic state,
so pass it to intel_dp_start_link_train(). In case of SST where
retraining still happens by calling this function directly instead of a
m
Simplify things by retraining a DP link if a bad link is detected in the
connector detect handler from the encoder's check link state work,
similarly to how this is done after a modeset link training failure.
v2: Add TODO: comment to remove the detect-time link state check.
(Ville)
Cc: Ville
Add a connector debugfs entry showing if link retraining is disabled.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_dp_link_training.c | 22 +++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/
Add a connector debugfs entry to force retrain an active link. This can
be used to test both custom link parameters (previously forced via the
force_link_rate/lane_count entries) or link train failure scenarios
(previously forced via the force_link_training_failure entry). The entry
will autoreset
Reduce the link parameters after a link training failure for MST
outputs, similarly to how this is done for SST.
For now allow the reduction only by staying in the 8b/10b vs. 128b/132b
mode. Enabling the mode switch is left for a follow-up patchset, after
taking measures ensuring that the mode swi
Add a connector debugfs entry to force a failure during the following
1-2 link training. The entry will auto-reset after the specified link
training events are complete.
v2: Add the entry from intel_dp_link_training.c (Jani)
v3: Lock connection_mutex only for the required intel_dp state. (Ville)
After a link training failure if the link parameters can't be further
reduced, there is no point in trying to retrain the link in the driver.
This avoids excessive retrain attempts after detecting a bad link, for
instance while handling MST HPD IRQs, which is likely redundant as the
link training f
Send a modeset-retry uevent to all connectors in the same MST topology
after a link training failure and reduction of the link parameters. This
matches the way the same uevent is sent after a DP tunnel BW allocation
failure.
v2: Add NOTE that the atomic state may not be valid for SST links and
Try to maintain the current link parameters by retrying the link
training with unchanged link parameters before reducing these parameters
(sending an uevent to userspace to retrain the link instead).
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_types.h| 2 ++
drive
Instead of direct calls to the link train functions, retrain the link
via a commit modeset. The direct call means that the output port will be
disabled/re-enabled while the rest of the pipeline (transcoder) is
active, which doesn't seem to work on MST at least. It leads to
underruns and black scree
Factor out a function to modeset commit a set of pipes, which a later
patch will reuse for DP link retraining.
Reviewed-by: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 31 +-
drivers/gpu/drm/i915/display/intel_display.c | 34
Reset the flag indicating an active link after disabling an MST link,
similarly to how this is done for SST outputs. This avoids trying to
retrain an MST link while its disabled.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++
1 file changed, 3 insertions(+)
di
Simplify things by retraining a DP link if a bad link is detected in the
hotplug handler from the encoder's check link state work, similarly to
how this is done after a modeset link training failure.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/g4x_dp.c| 20 +---
Move the functions used to reduce the link parameters during link
training to intel_dp_link_training.c .
Reviewed-by: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 76 +--
drivers/gpu/drm/i915/display/intel_dp.h | 4 +-
.../drm
Recheck the link state after a passing link training, with a 2 sec delay
to account for cases where the link goes bad following the link training
and the sink doesn't report this via an HPD IRQ.
The delayed work added here will be also used by a later patch after a
failed link training to try to r
Reduce the indentation in intel_dp_get_link_train_fallback_values() by
adding separate helpers to reduce the link rate and lane count. Also
simplify things by passing crtc_state to the function.
This also prepares for later patches in the patchset adding a limitation
on how the link params are red
Symbols consisting of multiple (4) TU timeslots may get split across
MTPs when using 2 or 1 link lanes. Avoid this, as required by Bspec by
aligning the allocated TUs to 2 when using 2 lanes and 4 when using 1
lane.
Atm, we also have to align the PBNs used to allocate BW along the MST
path, since
For clarity move the link training parameters updated during link
training based on the pass/fail LT result under a substruct in intel_dp.
This prepares for later patches in this patchset adding similar params
here. Rename intel_dp_reset_max_link_params() to
intel_dp_reset_link_params() to better r
This is v3 of [1], addressing the review comments and adding R-bs from
Ville, the main changes being:
- Add the link check work to intel_encoder and the corresponding helper
functions to a new intel_encoder.c file. (Patch 7)
- Add documentation/asserts on intel_atomic_state being valid for MST
Looks good to me,
Reviewed-by: Manasi Navare
Manasi
On Wed, May 22, 2024 at 11:23 AM Ville Syrjälä
wrote:
>
> On Mon, May 20, 2024 at 09:58:01PM +0300, Imre Deak wrote:
> > Move the functions used to reduce the link parameters during link
> > training to intel_dp_link_training.c .
> >
> > Sign
== Series Details ==
Series: drm: add missing MODULE_DESCRIPTION() macros
URL : https://patchwork.freedesktop.org/series/134680/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14912 -> Patchwork_134680v1
Summary
---
*
== Series Details ==
Series: drm: add missing MODULE_DESCRIPTION() macros
URL : https://patchwork.freedesktop.org/series/134680/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
On Fri, 7 Jun 2024 18:25:35 +0300
Jani Nikula wrote:
Reviewed-by: Zhi Wang
> All callers of calc_index() pass 0 for the end parameter. Remove it.
>
> Cc: Zhenyu Wang
> Cc: Zhi Wang
> Cc: intel-gvt-...@lists.freedesktop.org
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/gvt/hand
On Tue, Jun 4, 2024 at 9:46 AM Jani Nikula wrote:
[Maybe slightly off-topic, ranty]
> Why do we think it's a good idea to increase and normalize the use of
> double-underscore function names across the kernel, like
> __match_string() in this case? It should mean "reserved for the
> implementatio
On x86, make allmodconfig && make W=1 C=1 reports:
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/gpu/drm/gud/gud.o
WARNING: modpost: missing MODULE_DESCRIPTION() in
drivers/gpu/drm/drm_panel_orientation_quirks.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/gpu/drm/drm_mipi
== Series Details ==
Series: drm/i915: PREEMPT_RT related fixups. (rev7)
URL : https://patchwork.freedesktop.org/series/95463/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/95463/revisions/7/mbox/ not
applied
Applying: drm/i915: Use preempt_disab
Hi Andi,
On 10/06/2024 13:10, Andi Shyti wrote:
Hi Tvrtko,
On Mon, Jun 10, 2024 at 12:42:31PM +0100, Tvrtko Ursulin wrote:
On 03/06/2024 17:20, Niemiec, Krzysztof wrote:
The test is trying to push the heartbeat frequency to the limit, which
might sometimes fail. Such a failure does not prov
Hi Tvrtko,
On Mon, Jun 10, 2024 at 12:42:31PM +0100, Tvrtko Ursulin wrote:
> On 03/06/2024 17:20, Niemiec, Krzysztof wrote:
> > The test is trying to push the heartbeat frequency to the limit, which
> > might sometimes fail. Such a failure does not provide valuable
> > information, because it does
Am 06.06.24 um 14:35 schrieb Jani Nikula:
Debug printing at DisplayID validation leads to lots of log spamming as
it's called at DisplayID iterators during EDID parsing. Remove it, and
replace with a less noisy message at connector EDID update.
Signed-off-by: Jani Nikula
Acked-by: Thomas Z
On 03/06/2024 17:20, Niemiec, Krzysztof wrote:
The test is trying to push the heartbeat frequency to the limit, which
might sometimes fail. Such a failure does not provide valuable
information, because it does not indicate that there is something
necessarily wrong with either the driver or the
On Fri, 7 Jun 2024 18:25:38 +0300
Jani Nikula wrote:
> Do not rely on having dev_priv local variable, pass it to the macro.
>
> Cc: Zhenyu Wang
> Cc: Zhi Wang
> Cc: intel-gvt-...@lists.freedesktop.org
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
> 1 fil
On Fri, 7 Jun 2024 18:25:37 +0300
Jani Nikula wrote:
> Range is a bit odd name for what really is stride. Rename. Switch to
> u32 while at it.
>
> Cc: Zhenyu Wang
> Cc: Zhi Wang
> Cc: intel-gvt-...@lists.freedesktop.org
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/gvt/handlers.
On Fri, 7 Jun 2024 18:25:36 +0300
Jani Nikula wrote:
> In order to be able to use the proper register macros instead of the
> underscore prefixed ones, pass i915_reg_t for the calc_index()
> parameters.
>
> Side note: DSPSURF is really about planes, not pipes. Fixed stride
> doesn't work for pl
On Sun, 09 Jun 2024 11:42:53 -0700, Jeff Johnson wrote:
> On x86, make allmodconfig && make W=1 C=1 reports:
> WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/gpu/drm/gud/gud.o
> WARNING: modpost: missing MODULE_DESCRIPTION() in
> drivers/gpu/drm/drm_panel_orientation_quirks.o
> WARNING:
Hi Jani,
> -Original Message-
> From: Saarinen, Jani
> Sent: Monday, June 10, 2024 2:28 PM
> To: Saarinen, Jani ; Borah, Chaitanya Kumar
> ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar
> Subject: RE: [core-for-CI PATCH] Revert "e1000e: move force SMBUS near the
> end of
== Series Details ==
Series: drm/i915/panelreplay: Panel replay workaround with VRR (rev6)
URL : https://patchwork.freedesktop.org/series/129632/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14905 -> Patchwork_129632v6
Sum
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, June 7, 2024 7:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH 00/13] Panel Replay eDP prepare
>
> This is a subset of "Panel Replay eDP" patch set. It con
Hi Andi,
On 6/7/2024 4:51 PM, Andi Shyti wrote:
The forcewake count and domains listing is multi process critical
and the uncore provides a spinlock for such cases.
Lock the forcewake evaluation section in the fw_domains_show()
debugfs interface.
Signed-off-by: Andi Shyti
Needs a Fixes tag,
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of
> Saarinen, Jani
> Sent: Monday, 10 June 2024 11.23
> To: Borah, Chaitanya Kumar ; intel-
> g...@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar
> Subject: RE: [core-for-CI PATCH] Revert "e1000e: move force SMBUS near the
> end of
Panel Replay VSC SDP not getting sent when VRR is enabled
and W1 and W2 are 0. So Program Set Context Latency in
TRANS_SET_CONTEXT_LATENCY register to at least a value of 1.
HSD: 14015406119
v1: Initial version.
v2: Update timings stored in adjusted_mode struct. [Ville]
v3: Add WA in compute_conf
== Series Details ==
Series: Revert "e1000e: move force SMBUS near the end of enable_ulp function"
URL : https://patchwork.freedesktop.org/series/134664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14905 -> Patchwork_134664v1
=
== Series Details ==
Series: Revert "e1000e: move force SMBUS near the end of enable_ulp function"
URL : https://patchwork.freedesktop.org/series/134664/
State : warning
== Summary ==
Error: dim checkpatch failed
0a0dca1b254f Revert "e1000e: move force SMBUS near the end of enable_ulp
functio
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of
> Chaitanya Kumar Borah
> Sent: Monday, 10 June 2024 10.46
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar
> Subject: [core-for-CI PATCH] Revert "e1000e: move force SMBUS near the end
> of enable_ulp function"
>
== Series Details ==
Series: Implement CMRR Support (rev17)
URL : https://patchwork.freedesktop.org/series/126443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14905 -> Patchwork_126443v17
Summary
---
**SUCCESS**
== Series Details ==
Series: Implement CMRR Support (rev17)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Implement CMRR Support (rev17)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
710878293708 drm/i915: Update indentation for VRR registers and bits
-:56: WARNING:LONG_LINE: line length of 101 exceeds
This reverts commit bfd546a552e140b0a4c8a21527c39d6d21addb28.
The commit seems to cause problems in suspend-resume tests
[212.204897] e1000e :00:1f.6: PM: pci_pm_suspend(): e1000e_pm_suspend
[e1000e] returns -2
[212.204928] e1000e :00:1f.6: PM: dpm_run_callback(): pci_pm_suspend
returns
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/inte
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
with VRR timing generator or not. Make CMRR as s
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
--v3:
- vrr.enable and cmrr.enable check together is not required as both
will be true at the same point in time. (Ankit)
-
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
Acked-by: Maxime Ripard
---
include/drm/display/drm_
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 111 ++
drivers/gpu/drm/i915/i915_
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
--v2:
- Keep XELPD_VRR_CTL_VRR_GUARDBAND(x) to avoid readability (Ankit).
- Fix all indentation related VRR registers and bits instead of
checkpatch one.
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enab
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based o
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame dro
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